sneaxiy
6 years ago
commit
48324c32f2
@ -1,6 +1,8 @@
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include(operators)
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register_operators(EXCLUDES fusion_transpose_flatten_concat_op)
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register_operators(EXCLUDES fusion_transpose_flatten_concat_op fusion_conv_inception_op)
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if (WITH_GPU)
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op_library(fusion_transpose_flatten_concat_op)
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op_library(fusion_conv_inception_op)
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file(APPEND ${pybind_file} "USE_CUDA_ONLY_OP(fusion_transpose_flatten_concat);\n")
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file(APPEND ${pybind_file} "USE_CUDA_ONLY_OP(conv2d_inception_fusion);\n")
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endif()
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@ -0,0 +1,110 @@
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/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include <string>
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#include <vector>
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#include "paddle/fluid/framework/op_registry.h"
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#ifdef PADDLE_WITH_CUDA
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#include "paddle/fluid/platform/cudnn_helper.h"
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#endif
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namespace paddle {
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namespace operators {
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class ConvInceptionFusionOp : public framework::OperatorWithKernel {
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public:
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using framework::OperatorWithKernel::OperatorWithKernel;
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void InferShape(framework::InferShapeContext* ctx) const override {
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// 1 x
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auto in_dims = ctx->GetInputDim("Input");
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// 4 filters
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auto w_dims = ctx->GetInputsDim("Filter");
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PADDLE_ENFORCE(in_dims.size(), 4, "Conv intput should be 4-D tensor.");
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PADDLE_ENFORCE_EQ(w_dims.size(), 4, "There should be 4 filters");
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PADDLE_ENFORCE_EQ(w_dims[0][1], in_dims[1]);
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PADDLE_ENFORCE_EQ(w_dims[1][1], in_dims[1]);
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int n = in_dims[0];
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// compute output channel
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// 1st channel
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int c = w_dims[0][0];
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// add 2nd channel
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c += (w_dims[1][0] - w_dims[2][1] * 2);
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// add 3rd channel
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c += (w_dims[2][0] - w_dims[3][1]);
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// add 4-th channel
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c += w_dims[3][0];
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int h = in_dims[2];
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int w = in_dims[3];
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ctx->SetOutputDim("Output", {n, c, h, w});
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}
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protected:
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framework::OpKernelType GetExpectedKernelType(
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const framework::ExecutionContext& ctx) const override {
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return framework::OpKernelType(
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ctx.Input<framework::LoDTensor>("Input")->type(), ctx.device_context());
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}
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};
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class ConvInceptionFusionOpMaker : public framework::OpProtoAndCheckerMaker {
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protected:
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void Make() override {
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AddInput("Input", "(Tensor) NCHW layout.");
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AddInput("Filter", "(vector<Tensor>) 4 aggregated filters").AsDuplicable();
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AddInput("Bias", "(vector<Tensor>) it's lenght is equal to Filter")
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.AsDuplicable();
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AddOutput("Output",
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"(Tensor) The output tensor of convolution operator. "
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"The format of output tensor is also NCHW.");
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AddOutput("TempOutput", "").AsDuplicable();
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AddAttr<std::string>(
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"pooling_type",
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"(string), pooling type, can be \"max\" for max-pooling "
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"and \"avg\" for average-pooling.")
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.InEnum({"max", "avg"});
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AddAttr<bool>(
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"exclusive",
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"(bool, default True) When true, will exclude the zero-padding in the "
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"averaging calculating, otherwise, include the zero-padding. Note, it "
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"is only used when pooling_type is avg. The defalut is True.")
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.SetDefault(true);
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AddAttr<std::string>(
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"activation",
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"The activation type can be 'identity', 'sigmoid', 'relu', 'relu6' "
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"'relux' , 'tanh', 'band_pass'")
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.SetDefault("relu");
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AddAttr<int>("workspace_size_MB",
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"Only used in cudnn kernel. Need set use_cudnn to true."
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"workspace size for cudnn, in MB, "
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"workspace is a section of GPU memory which will be "
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"allocated/freed each time the operator runs, larger "
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"workspace size can increase performance but also requires "
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"better hardware. This size should be chosen carefully.")
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.SetDefault(4096);
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AddComment(R"DOC(
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)DOC");
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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REGISTER_OPERATOR(conv2d_inception_fusion, ops::ConvInceptionFusionOp,
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ops::ConvInceptionFusionOpMaker,
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paddle::framework::EmptyGradOpMaker);
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