Zhuoyuan
7 years ago
committed by
GitHub
commit
6d649d9ebd
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/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserve.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/operators/conv2d_transpose_op.h"
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namespace paddle {
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namespace operators {
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class CudnnConv2DTransposeOpMaker : public Conv2DTransposeOpMaker {
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public:
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CudnnConv2DTransposeOpMaker(framework::OpProto* proto,
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framework::OpAttrChecker* op_checker)
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: Conv2DTransposeOpMaker(proto, op_checker) {
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AddAttr<std::vector<int>>("dilations", "dilations of convolution operator.")
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.SetDefault(std::vector<int>{1, 1});
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AddAttr<int>("workspace_size_MB",
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"workspace size for cudnn, in MB, "
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"workspace is a section of GPU memory which will be "
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"allocated/freed each time the operator runs, larger "
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"workspace size can increase performance but also requires "
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"better hardward. This size should be carefully setted.")
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.SetDefault(4096);
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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REGISTER_OP(conv2d_transpose_cudnn, ops::Conv2DTransposeOp,
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ops::CudnnConv2DTransposeOpMaker, conv2d_transpose_cudnn_grad,
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ops::Conv2DTransposeOpGrad);
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REGISTER_OP_CPU_KERNEL(
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conv2d_transpose_cudnn,
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ops::GemmConv2DTransposeKernel<paddle::platform::CPUPlace, float>);
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REGISTER_OP_CPU_KERNEL(
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conv2d_transpose_cudnn_grad,
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ops::GemmConv2DTransposeGradKernel<paddle::platform::CPUPlace, float>);
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@ -0,0 +1,240 @@
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/* Copyright (c) 2016 PaddlePaddle Authors All Rights Reserve.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/framework/eigen.h"
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#include "paddle/framework/op_registry.h"
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#include "paddle/memory/memory.h"
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#include "paddle/operators/conv2d_transpose_op.h"
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#include "paddle/platform/assert.h"
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#include "paddle/platform/cudnn_helper.h"
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namespace paddle {
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namespace operators {
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using Tensor = framework::Tensor;
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using ScopedTensorDescriptor = platform::ScopedTensorDescriptor;
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using ScopedFilterDescriptor = platform::ScopedFilterDescriptor;
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using ScopedConvolutionDescriptor = platform::ScopedConvolutionDescriptor;
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using DataLayout = platform::DataLayout;
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using CUDADeviceContext = platform::CUDADeviceContext;
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static constexpr size_t kConvCudnnWorkspaceLimitBytes = 1024 * 1024 * 1024;
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template <typename T>
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class CudnnConvTransposeOpKernel : public framework::OpKernel<T> {
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public:
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void Compute(const framework::ExecutionContext& ctx) const override {
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PADDLE_ENFORCE(platform::is_gpu_place(ctx.GetPlace()),
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"It must use GPUPlace.");
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auto* input = ctx.Input<Tensor>("Input");
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auto* filter = ctx.Input<Tensor>("Filter");
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auto* output = ctx.Output<Tensor>("Output");
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std::vector<int> strides = ctx.Attr<std::vector<int>>("strides");
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std::vector<int> paddings = ctx.Attr<std::vector<int>>("paddings");
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// cudnn v5 does not support dilations
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std::vector<int> dilations = ctx.Attr<std::vector<int>>("dilations");
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int user_workspace_size = ctx.Attr<int>("workspace_size_MB");
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const T* input_data = input->data<T>();
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const T* filter_data = filter->data<T>();
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T* output_data = output->mutable_data<T>(ctx.GetPlace());
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// ------------------- cudnn descriptors ---------------------
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ScopedTensorDescriptor input_desc;
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ScopedTensorDescriptor output_desc;
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ScopedFilterDescriptor filter_desc;
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ScopedConvolutionDescriptor conv_desc;
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DataLayout layout = DataLayout::kNCHW;
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// N, M, H, W
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cudnnTensorDescriptor_t cudnn_input_desc = input_desc.descriptor<T>(
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layout, framework::vectorize2int(input->dims()));
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// N, C, O_h, O_w
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cudnnTensorDescriptor_t cudnn_output_desc = output_desc.descriptor<T>(
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layout, framework::vectorize2int(output->dims()));
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// M, C, K_h, K_w
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cudnnFilterDescriptor_t cudnn_filter_desc = filter_desc.descriptor<T>(
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layout, framework::vectorize2int(filter->dims()));
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cudnnConvolutionDescriptor_t cudnn_conv_desc =
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conv_desc.descriptor<T>(paddings, strides, dilations);
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// ------------------- cudnn conv workspace ---------------------
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void* cudnn_workspace = nullptr;
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size_t workspace_size_in_bytes; // final workspace to allocate.
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size_t workspace_size_limit = kConvCudnnWorkspaceLimitBytes;
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if (user_workspace_size > 0) {
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workspace_size_limit = user_workspace_size * 1024 * 1024;
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}
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// ------------------- cudnn conv algorithm ---------------------
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cudnnConvolutionBwdDataAlgo_t algo;
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auto handle = ctx.cuda_device_context().cudnn_handle();
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// Get the algorithm
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PADDLE_ENFORCE(platform::dynload::cudnnGetConvolutionBackwardDataAlgorithm(
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handle, cudnn_filter_desc, cudnn_input_desc, cudnn_conv_desc,
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// dxDesc: Handle to the previously initialized output tensor
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// descriptor.
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cudnn_output_desc, CUDNN_CONVOLUTION_BWD_DATA_SPECIFY_WORKSPACE_LIMIT,
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workspace_size_limit, &algo));
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// get workspace size able to allocate
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PADDLE_ENFORCE(
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platform::dynload::cudnnGetConvolutionBackwardDataWorkspaceSize(
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handle, cudnn_filter_desc, cudnn_input_desc, cudnn_conv_desc,
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cudnn_output_desc, algo, &workspace_size_in_bytes));
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// Allocate on GPU memory
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platform::GPUPlace gpu = boost::get<platform::GPUPlace>(ctx.GetPlace());
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cudnn_workspace = paddle::memory::Alloc(gpu, workspace_size_in_bytes);
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// ------------------- cudnn conv transpose forward ---------------------
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T alpha = 1.0f, beta = 0.0f;
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PADDLE_ENFORCE(platform::dynload::cudnnConvolutionBackwardData(
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handle, &alpha, cudnn_filter_desc, filter_data, cudnn_input_desc,
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input_data, cudnn_conv_desc, algo, cudnn_workspace,
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workspace_size_in_bytes, &beta, cudnn_output_desc, output_data));
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// Release the cudnn workspace
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paddle::memory::Free(gpu, cudnn_workspace);
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}
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};
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template <typename T>
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class CudnnConvTransposeGradOpKernel : public framework::OpKernel<T> {
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public:
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void Compute(const framework::ExecutionContext& ctx) const override {
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PADDLE_ENFORCE(platform::is_gpu_place(ctx.GetPlace()),
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"It must use GPUPlace.");
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auto input = ctx.Input<Tensor>("Input");
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auto filter = ctx.Input<Tensor>("Filter");
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auto output_grad = ctx.Input<Tensor>(framework::GradVarName("Output"));
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auto input_grad = ctx.Output<Tensor>(framework::GradVarName("Input"));
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auto filter_grad = ctx.Output<Tensor>(framework::GradVarName("Filter"));
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const T* input_data = input->data<T>();
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const T* output_grad_data = output_grad->data<T>();
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const T* filter_data = filter->data<T>();
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std::vector<int> strides = ctx.Attr<std::vector<int>>("strides");
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std::vector<int> paddings = ctx.Attr<std::vector<int>>("paddings");
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// cudnn v5 does not support dilations
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std::vector<int> dilations = ctx.Attr<std::vector<int>>("dilations");
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int user_workspace_size = ctx.Attr<int>("workspace_size_MB");
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// ------------------- cudnn descriptors ---------------------
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ScopedTensorDescriptor input_desc;
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ScopedTensorDescriptor output_desc;
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ScopedFilterDescriptor filter_desc;
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ScopedConvolutionDescriptor conv_desc;
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DataLayout layout = DataLayout::kNCHW;
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// Input: (N, M, H, W)
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cudnnTensorDescriptor_t cudnn_input_desc = input_desc.descriptor<T>(
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layout, framework::vectorize2int(input->dims()));
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// Output: (N, C, O_H, O_W)
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cudnnTensorDescriptor_t cudnn_output_desc = output_desc.descriptor<T>(
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layout, framework::vectorize2int(output_grad->dims()));
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// Filter (M, C, K_H, K_W)
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cudnnFilterDescriptor_t cudnn_filter_desc = filter_desc.descriptor<T>(
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layout, framework::vectorize2int(filter->dims()));
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cudnnConvolutionDescriptor_t cudnn_conv_desc =
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conv_desc.descriptor<T>(paddings, strides, dilations);
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// ------------------- cudnn backward algorithm ---------------------
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cudnnConvolutionFwdAlgo_t data_algo;
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cudnnConvolutionBwdFilterAlgo_t filter_algo;
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size_t bwd_filter_ws_size, fwd_ws_size;
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size_t workspace_size_in_bytes = 0;
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size_t workspace_size_limit = kConvCudnnWorkspaceLimitBytes;
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if (user_workspace_size > 0) {
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workspace_size_limit = user_workspace_size * 1024 * 1024;
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}
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auto handle = ctx.cuda_device_context().cudnn_handle();
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if (input_grad) {
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// choose backward algorithm for data
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PADDLE_ENFORCE(platform::dynload::cudnnGetConvolutionForwardAlgorithm(
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handle, cudnn_output_desc, cudnn_filter_desc, cudnn_conv_desc,
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cudnn_input_desc, CUDNN_CONVOLUTION_FWD_SPECIFY_WORKSPACE_LIMIT,
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workspace_size_limit, &data_algo));
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PADDLE_ENFORCE(platform::dynload::cudnnGetConvolutionForwardWorkspaceSize(
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handle, cudnn_output_desc, cudnn_filter_desc, cudnn_conv_desc,
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cudnn_input_desc, data_algo, &fwd_ws_size));
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workspace_size_in_bytes = std::max(workspace_size_in_bytes, fwd_ws_size);
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}
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if (filter_grad) {
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// choose backward algorithm for filter
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PADDLE_ENFORCE(
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platform::dynload::cudnnGetConvolutionBackwardFilterAlgorithm(
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handle, cudnn_output_desc, cudnn_input_desc, cudnn_conv_desc,
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cudnn_filter_desc,
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CUDNN_CONVOLUTION_BWD_FILTER_SPECIFY_WORKSPACE_LIMIT,
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workspace_size_limit, &filter_algo));
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// get workspace for backwards filter algorithm
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PADDLE_ENFORCE(
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platform::dynload::cudnnGetConvolutionBackwardFilterWorkspaceSize(
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handle, cudnn_output_desc, cudnn_input_desc, cudnn_conv_desc,
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cudnn_filter_desc, filter_algo, &bwd_filter_ws_size));
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workspace_size_in_bytes =
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std::max(workspace_size_in_bytes, bwd_filter_ws_size);
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}
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// ------------------- cudnn conv workspace ---------------------
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// Already on GPU
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void* cudnn_workspace = nullptr;
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platform::GPUPlace gpu = boost::get<platform::GPUPlace>(ctx.GetPlace());
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cudnn_workspace = paddle::memory::Alloc(gpu, workspace_size_in_bytes);
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// ------------------- cudnn conv backward data ---------------------
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// FIXME(typhoonzero): template type T may not be the same as cudnn call.
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T alpha = 1.0f, beta = 0.0f;
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if (input_grad) {
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T* input_grad_data = input_grad->mutable_data<T>(ctx.GetPlace());
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auto t = framework::EigenVector<T>::Flatten(*input_grad);
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t.device(ctx.GetEigenDevice<platform::GPUPlace>()) =
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t.constant(static_cast<T>(0));
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PADDLE_ENFORCE(platform::dynload::cudnnConvolutionForward(
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handle, &alpha, cudnn_output_desc, output_grad_data,
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cudnn_filter_desc, filter_data, cudnn_conv_desc, data_algo,
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cudnn_workspace, workspace_size_in_bytes, &beta, cudnn_input_desc,
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input_grad_data));
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}
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// ------------------- cudnn conv backward filter ---------------------
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if (filter_grad) {
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T* filter_grad_data = filter_grad->mutable_data<T>(ctx.GetPlace());
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auto t = framework::EigenVector<T>::Flatten(*filter_grad);
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t.device(ctx.GetEigenDevice<platform::GPUPlace>()) =
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t.constant(static_cast<T>(0));
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// Gradient with respect to the filter
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PADDLE_ENFORCE(platform::dynload::cudnnConvolutionBackwardFilter(
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handle, &alpha, cudnn_output_desc, output_grad_data, cudnn_input_desc,
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input_data, cudnn_conv_desc, filter_algo, cudnn_workspace,
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workspace_size_in_bytes, &beta, cudnn_filter_desc, filter_grad_data));
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}
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// Release the cudnn workspace
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paddle::memory::Free(gpu, cudnn_workspace);
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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REGISTER_OP_GPU_KERNEL(conv2d_transpose_cudnn,
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ops::CudnnConvTransposeOpKernel<float>);
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REGISTER_OP_GPU_KERNEL(conv2d_transpose_cudnn_grad,
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ops::CudnnConvTransposeGradOpKernel<float>);
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