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/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserve.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/fluid/operators/nearest_neighbor_interp_op.h"
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#include <vector>
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#include "paddle/fluid/framework/op_registry.h"
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namespace paddle {
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namespace operators {
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using framework::Tensor;
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class NearestNeighborInterpOp : public framework::OperatorWithKernel {
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public:
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using framework::OperatorWithKernel::OperatorWithKernel;
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protected:
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void InferShape(framework::InferShapeContext* ctx) const override {
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PADDLE_ENFORCE(ctx->HasInput("X"),
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"Input(X) of BilinearInterOp should not be null.");
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PADDLE_ENFORCE(ctx->HasOutput("Out"),
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"Output(Out) of BilinearInterOp should not be null.");
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auto dim_x = ctx->GetInputDim("X"); // NCHW format
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int out_h = ctx->Attrs().Get<int>("out_h");
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int out_w = ctx->Attrs().Get<int>("out_w");
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PADDLE_ENFORCE_EQ(dim_x.size(), 4, "X's dimension must be 4");
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if (ctx->HasInput("OutSize")) {
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auto out_size_dim = ctx->GetInputDim("OutSize");
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PADDLE_ENFORCE_EQ(out_size_dim.size(), 1,
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"OutSize's dimension size must be 1");
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PADDLE_ENFORCE_EQ(out_size_dim[0], 2, "OutSize's dim[0] must be 2");
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}
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std::vector<int64_t> dim_out({dim_x[0], dim_x[1], out_h, out_w});
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ctx->SetOutputDim("Out", framework::make_ddim(dim_out));
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}
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protected:
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framework::OpKernelType GetExpectedKernelType(
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const framework::ExecutionContext& ctx) const override {
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return framework::OpKernelType(
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framework::ToDataType(ctx.Input<Tensor>("X")->type()), ctx.GetPlace());
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}
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};
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class NearestNeighborInterpOpMaker : public framework::OpProtoAndCheckerMaker {
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public:
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void Make() override {
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AddInput("X",
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"The input tensor of nearest neighbor interpolation, "
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"This is a 4-D tensor with shape of (N x C x h x w)");
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AddInput("OutSize",
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"This is a 1-D tensor with two number. "
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"The first number is height and the second number is width.")
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.AsDispensable();
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AddOutput("Out", "The dimension of output is (N x C x out_h x out_w)");
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AddAttr<int>("out_h", "output height of bilinear interpolation op.");
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AddAttr<int>("out_w", "output width of bilinear interpolation op.");
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AddComment(R"DOC(
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Nearest neighbor interpolation is to perform nearest neighbor interpolation
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in bot the 3rd dimention(in height direction) and the 4th dimention(in width
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direction) on input tensor.
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For details, please refer to Wikipedia:
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https://en.wikipedia.org/wiki/Nearest-neighbor_interpolation
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)DOC");
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}
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};
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class NearestNeighborInterpOpGrad : public framework::OperatorWithKernel {
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public:
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using framework::OperatorWithKernel::OperatorWithKernel;
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protected:
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void InferShape(framework::InferShapeContext* ctx) const override {
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PADDLE_ENFORCE(ctx->HasInput("X"), "Input(X) should not be null");
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PADDLE_ENFORCE(ctx->HasInput(framework::GradVarName("Out")),
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"Input(Out@GRAD) should not be null");
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auto dim_x = ctx->GetInputDim("X");
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if (ctx->HasOutput(framework::GradVarName("X"))) {
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ctx->SetOutputDim(framework::GradVarName("X"), dim_x);
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}
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}
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framework::OpKernelType GetExpectedKernelType(
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const framework::ExecutionContext& ctx) const override {
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return framework::OpKernelType(
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framework::ToDataType(ctx.Input<Tensor>("X")->type()), ctx.GetPlace());
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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REGISTER_OPERATOR(nearest_neighbor_interp, ops::NearestNeighborInterpOp,
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ops::NearestNeighborInterpOpMaker,
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paddle::framework::DefaultGradOpDescMaker<true>);
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REGISTER_OPERATOR(nearest_neighbor_interp_grad,
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ops::NearestNeighborInterpOpGrad);
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REGISTER_OP_CPU_KERNEL(nearest_neighbor_interp,
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ops::NearestNeighborInterpKernel<float>,
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ops::NearestNeighborInterpKernel<uint8_t>);
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REGISTER_OP_CPU_KERNEL(nearest_neighbor_interp_grad,
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ops::NearestNeighborInterpGradKernel<float>);
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/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserve.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/fluid/operators/nearest_neighbor_interp_op.h"
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#include "paddle/fluid/platform/cuda_primitives.h"
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namespace paddle {
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namespace operators {
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template <typename T, size_t D, int MajorType = Eigen::RowMajor,
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typename IndexType = Eigen::DenseIndex>
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using EigenTensor = framework::EigenTensor<T, D, MajorType, IndexType>;
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using framework::Tensor;
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template <typename T>
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__global__ void KeBilinearInterpFw(
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const T* in, const size_t in_img_h, const size_t in_img_w,
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const size_t input_h, const size_t input_w, T* out, const size_t out_img_h,
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const size_t out_img_w, const size_t output_h, const size_t output_w,
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const size_t num_channels, const T ratio_h, const T ratioW) {
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int nthreads = output_h * output_w;
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int tid = blockIdx.x * blockDim.x + threadIdx.x;
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if (tid < nthreads) {
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int out_id_h = tid / output_w;
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int out_id_w = tid % output_w;
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int in_img_size = input_w / num_channels;
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int out_img_size = output_w / num_channels;
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int channel_id = out_id_w / out_img_size;
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int out_img_idy = (out_id_w % out_img_size) / out_img_w;
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int in_img_idy = ratio_h * out_img_idy;
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int h_id = (in_img_idy < in_img_h - 1) ? 1 : 0;
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T h1lambda = ratio_h * out_img_idy - in_img_idy;
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T h2lambda = 1.f - h1lambda;
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int out_img_idx = tid % out_img_w;
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int in_img_idx = ratioW * out_img_idx;
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int w_id = (in_img_idx < in_img_w - 1) ? 1 : 0;
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T w1lambda = ratioW * out_img_idx - in_img_idx;
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T w2lambda = 1.f - w1lambda;
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const T* in_pos = &in[out_id_h * input_w + channel_id * in_img_size +
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in_img_idy * in_img_w + in_img_idx];
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// bilinear interpolation
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out[out_id_h * output_w + out_id_w] =
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h2lambda * (w2lambda * in_pos[0] + w1lambda * in_pos[w_id]) +
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h1lambda * (w2lambda * in_pos[h_id * in_img_w] +
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w1lambda * in_pos[h_id * in_img_w + w_id]);
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}
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}
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template <typename T>
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__global__ void KeBilinearInterpBw(
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T* in, const size_t in_img_h, const size_t in_img_w, const size_t input_h,
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const size_t input_w, const T* out, const size_t out_img_h,
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const size_t out_img_w, const size_t output_h, const size_t output_w,
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const size_t num_channels, const T ratio_h, const T ratioW) {
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int nthreads = output_h * output_w;
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int tid = blockIdx.x * blockDim.x + threadIdx.x;
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if (tid < nthreads) {
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int out_id_h = tid / output_w;
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int out_id_w = tid % output_w;
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int in_img_size = input_w / num_channels;
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int out_img_size = output_w / num_channels;
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int channel_id = out_id_w / out_img_size;
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int out_img_idy = (out_id_w % out_img_size) / out_img_w;
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int in_img_idy = ratio_h * out_img_idy;
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int h_id = (in_img_idy < in_img_h - 1) ? 1 : 0;
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T h1lambda = ratio_h * out_img_idy - in_img_idy;
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T h2lambda = 1.f - h1lambda;
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int out_img_idx = tid % out_img_w;
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int in_img_idx = ratioW * out_img_idx;
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int w_id = (in_img_idx < in_img_w - 1) ? 1 : 0;
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T w1lambda = ratioW * out_img_idx - in_img_idx;
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T w2lambda = 1.f - w1lambda;
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T* in_pos = &in[out_id_h * input_w + channel_id * in_img_size +
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in_img_idy * in_img_w + in_img_idx];
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const T* out_pos = &out[out_id_h * output_w + out_id_w];
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atomicAdd(&in_pos[0], h2lambda * w2lambda * out_pos[0]);
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atomicAdd(&in_pos[w_id], h2lambda * w1lambda * out_pos[0]);
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atomicAdd(&in_pos[h_id * in_img_w], h1lambda * w2lambda * out_pos[0]);
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atomicAdd(&in_pos[h_id * in_img_w + w_id],
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h1lambda * w1lambda * out_pos[0]);
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}
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}
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template <typename T>
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class NearestNeighborInterpOpCUDAKernel : public framework::OpKernel<T> {
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public:
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void Compute(const framework::ExecutionContext& ctx) const override {
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PADDLE_ENFORCE(platform::is_gpu_place(ctx.GetPlace()),
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"This kernel only runs on GPU device.");
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auto* input_t = ctx.Input<Tensor>("X"); // float tensor
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auto* output_t = ctx.Output<Tensor>("Out"); // float tensor
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auto* input = input_t->data<T>();
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int out_h = ctx.Attr<int>("out_h");
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int out_w = ctx.Attr<int>("out_w");
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auto out_dims = output_t->dims();
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auto out_size_t = ctx.Input<Tensor>("OutSize");
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if (out_size_t != nullptr) {
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Tensor sizes;
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framework::TensorCopy(*out_size_t, platform::CPUPlace(), &sizes);
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auto size_data = sizes.data<int>();
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out_h = size_data[0];
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out_w = size_data[1];
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}
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auto* output = output_t->mutable_data<T>(
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{out_dims[0], out_dims[1], out_h, out_w}, ctx.GetPlace());
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int batch_size = input_t->dims()[0];
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int channels = input_t->dims()[1];
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int in_h = input_t->dims()[2];
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int in_w = input_t->dims()[3];
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int in_hw = in_h * in_w;
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int out_hw = out_h * out_w;
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int in_chw = channels * in_hw;
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int out_chw = channels * out_hw;
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T ratio_h = (out_h > 1) ? static_cast<T>(in_h - 1) / (out_h - 1) : 0.f;
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T ratio_w = (out_w > 1) ? static_cast<T>(in_w - 1) / (out_w - 1) : 0.f;
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if (in_h == out_h && in_w == out_w) {
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memcpy(output, input, input_t->numel() * sizeof(T));
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} else {
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int threadNum = batch_size * out_chw;
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int blocks = (threadNum + 1024 - 1) / 1024;
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KeBilinearInterpFw<
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T><<<blocks, 1024, 0, ctx.cuda_device_context().stream()>>>(
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input, in_h, in_w, batch_size, in_chw, output, out_h, out_w,
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batch_size, out_chw, channels, ratio_h, ratio_w);
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}
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}
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};
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template <typename T>
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class NearestNeighborInterpGradOpCUDAKernel : public framework::OpKernel<T> {
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public:
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void Compute(const framework::ExecutionContext& ctx) const override {
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auto* d_input_t = ctx.Output<Tensor>(framework::GradVarName("X"));
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auto* d_output_t = ctx.Input<Tensor>(framework::GradVarName("Out"));
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auto* d_output = d_output_t->data<T>();
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auto* d_input = d_input_t->mutable_data<T>(ctx.GetPlace());
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auto& device_ctx =
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ctx.template device_context<platform::CUDADeviceContext>();
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math::SetConstant<platform::CUDADeviceContext, T> zero;
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zero(device_ctx, d_input_t, static_cast<T>(0.0));
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int out_h = ctx.Attr<int>("out_h");
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int out_w = ctx.Attr<int>("out_w");
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auto out_size_t = ctx.Input<Tensor>("OutSize");
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if (out_size_t != nullptr) {
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Tensor sizes;
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framework::TensorCopy(*out_size_t, platform::CPUPlace(), &sizes);
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auto size_data = sizes.data<int>();
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out_h = size_data[0];
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out_w = size_data[1];
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}
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int batch_size = d_input_t->dims()[0];
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int channels = d_input_t->dims()[1];
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int in_h = d_input_t->dims()[2];
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int in_w = d_input_t->dims()[3];
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int in_hw = in_h * in_w;
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int out_hw = out_h * out_w;
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int in_chw = channels * in_hw;
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int out_chw = channels * out_hw;
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T ratio_h = (out_h > 1) ? static_cast<T>(in_h - 1) / (out_h - 1) : 0.f;
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T ratio_w = (out_w > 1) ? static_cast<T>(in_w - 1) / (out_w - 1) : 0.f;
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if (in_h == out_h && in_w == out_w) {
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memcpy(d_input, d_output, d_input_t->numel() * sizeof(T));
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} else {
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int threadNum = batch_size * out_chw;
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int blocks = (threadNum + 1024 - 1) / 1024;
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KeBilinearInterpBw<
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T><<<blocks, 1024, 0, ctx.cuda_device_context().stream()>>>(
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d_input, in_h, in_w, batch_size, in_chw, d_output, out_h, out_w,
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batch_size, out_chw, channels, ratio_h, ratio_w);
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}
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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REGISTER_OP_CUDA_KERNEL(nearest_neighbor_interp,
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ops::NearestNeighborInterpOpCUDAKernel<float>);
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REGISTER_OP_CUDA_KERNEL(nearest_neighborinterp_grad,
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ops::NearestNeighborInterpGradOpCUDAKernel<float>);
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@ -0,0 +1,130 @@
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/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserve.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
|
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Unless required by applicable law or agreed to in writing, software
|
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distributed under the License is distributed on an "AS IS" BASIS,
|
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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See the License for the specific language governing permissions and
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limitations under the License. */
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#pragma once
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#include "paddle/fluid/framework/op_registry.h"
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#include "paddle/fluid/operators/math/math_function.h"
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namespace paddle {
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namespace operators {
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template <typename T, size_t D, int MajorType = Eigen::RowMajor,
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typename IndexType = Eigen::DenseIndex>
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using EigenTensor = framework::EigenTensor<T, D, MajorType, IndexType>;
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using Tensor = framework::Tensor;
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template <typename T>
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class NearestNeighborInterpKernel : public framework::OpKernel<T> {
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public:
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void Compute(const framework::ExecutionContext& ctx) const override {
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auto* input = ctx.Input<Tensor>("X");
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auto* output = ctx.Output<Tensor>("Out");
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int out_h = ctx.Attr<int>("out_h");
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int out_w = ctx.Attr<int>("out_w");
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auto out_size = ctx.Input<Tensor>("OutSize");
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if (out_size != nullptr) {
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auto out_size_data = out_size->data<int>();
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out_h = out_size_data[0];
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out_w = out_size_data[1];
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}
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const int in_n = input->dims()[0];
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const int in_c = input->dims()[1];
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const int in_h = input->dims()[2];
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const int in_w = input->dims()[3];
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output->mutable_data<T>({in_n, in_c, out_h, out_w}, ctx.GetPlace());
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auto& device_ctx =
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ctx.template device_context<platform::CPUDeviceContext>();
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math::SetConstant<platform::CPUDeviceContext, T> zero;
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zero(device_ctx, output, static_cast<T>(0.0));
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if (in_h == out_h && in_w == out_w) {
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framework::TensorCopy(*input, ctx.GetPlace(), output);
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return;
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}
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float ratio_h =
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(out_h > 1) ? static_cast<float>(in_h - 1) / (out_h - 1) : 0.f;
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float ratio_w =
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(out_w > 1) ? static_cast<float>(in_w - 1) / (out_w - 1) : 0.f;
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auto input_t = EigenTensor<T, 4>::From(*input);
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auto output_t = EigenTensor<T, 4>::From(*output);
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for (int k = 0; k < out_h; k++) { // loop for images
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for (int l = 0; l < out_w; l++) {
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int in_k = static_cast<int>(round(ratio_h * k));
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int in_l = static_cast<int>(round(ratio_w * l));
|
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for (int i = 0; i < in_n; i++) { // loop for batches
|
||||
for (int j = 0; j < in_c; j++) { // loop for channels
|
||||
output_t(i, j, k, l) = input_t(i, j, in_k, in_l);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
template <typename T>
|
||||
class NearestNeighborInterpGradKernel : public framework::OpKernel<T> {
|
||||
public:
|
||||
void Compute(const framework::ExecutionContext& ctx) const override {
|
||||
auto* input_grad = ctx.Output<Tensor>(framework::GradVarName("X"));
|
||||
auto* output_grad = ctx.Input<Tensor>(framework::GradVarName("Out"));
|
||||
|
||||
int out_h = ctx.Attr<int>("out_h");
|
||||
int out_w = ctx.Attr<int>("out_w");
|
||||
auto out_size = ctx.Input<Tensor>("OutSize");
|
||||
if (out_size != nullptr) {
|
||||
auto out_size_data = out_size->data<int>();
|
||||
out_h = out_size_data[0];
|
||||
out_w = out_size_data[1];
|
||||
}
|
||||
|
||||
const int in_n = input_grad->dims()[0];
|
||||
const int in_c = input_grad->dims()[1];
|
||||
const int in_h = input_grad->dims()[2];
|
||||
const int in_w = input_grad->dims()[3];
|
||||
|
||||
auto& device_ctx =
|
||||
ctx.template device_context<platform::CPUDeviceContext>();
|
||||
math::SetConstant<platform::CPUDeviceContext, T> zero;
|
||||
zero(device_ctx, input_grad, static_cast<T>(0.0));
|
||||
|
||||
if (in_h == out_h && in_w == out_w) {
|
||||
framework::TensorCopy(*output_grad, ctx.GetPlace(), input_grad);
|
||||
return;
|
||||
}
|
||||
|
||||
float ratio_h =
|
||||
(out_h > 1) ? static_cast<float>(in_h - 1) / (out_h - 1) : 0.f;
|
||||
float ratio_w =
|
||||
(out_w > 1) ? static_cast<float>(in_w - 1) / (out_w - 1) : 0.f;
|
||||
|
||||
auto input_grad_t = EigenTensor<T, 4>::From(*input_grad);
|
||||
auto output_grad_t = EigenTensor<T, 4>::From(*output_grad);
|
||||
for (int k = 0; k < out_h; k++) { // loop for images
|
||||
for (int l = 0; l < out_w; l++) {
|
||||
int in_k = static_cast<int>(round(ratio_h * k));
|
||||
int in_l = static_cast<int>(round(ratio_w * l));
|
||||
for (int i = 0; i < in_n; i++) { // loop for batches
|
||||
for (int j = 0; j < in_c; j++) { // loop for channels
|
||||
input_grad_t(i, j, in_k, in_l) += output_grad_t(i, j, k, l);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace operators
|
||||
} // namespace paddle
|
Loading…
Reference in new issue