fix typo words (#22653)

revert-22710-feature/integrated_ps_api
tianshuo78520a 5 years ago committed by GitHub
parent 6e7bfe30a6
commit d2ba91aad1
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@ -126,7 +126,7 @@ class Dataset {
virtual void DestroyPreLoadReaders() = 0;
// set preload thread num
virtual void SetPreLoadThreadNum(int thread_num) = 0;
// seperate train thread and dataset thread
// separate train thread and dataset thread
virtual void DynamicAdjustChannelNum(int channel_num) = 0;
virtual void DynamicAdjustReadersNum(int thread_num) = 0;
// set fleet send sleep seconds

@ -133,10 +133,10 @@ struct BuildStrategy {
// The picture is here:
// https://github.com/PaddlePaddle/Paddle/pull/17263#discussion_r285411396
bool use_hierarchical_allreduce_{false};
// Nccl ranks in a node when use hierarchical allreduce, it's setted to gpu
// Nccl ranks in a node when use hierarchical allreduce, it's set to gpu
// cards' number in most cases.
size_t hierarchical_allreduce_inter_nranks_{0};
// Nccl ranks bewteen nodes when use hierarchical allreduce, it's setted to
// Nccl ranks bewteen nodes when use hierarchical allreduce, it's set to
// nodes number.
size_t hierarchical_allreduce_exter_nranks_{0};

@ -33,7 +33,7 @@ namespace ir {
GET_IR_NODE(act_op); \
GET_IR_NODE(act_out);
// Inherient the basic infomation from `base_desc`, and modify some fields.
// Inherient the basic information from `base_desc`, and modify some fields.
framework::proto::OpDesc PrepareOpDesc(
const framework::proto::OpDesc& base_desc, const std::string& bias,
const std::string& bias1, const std::string& activation,

@ -31,7 +31,7 @@ namespace ir {
GET_IR_NODE(act_op); \
GET_IR_NODE(act_out);
// Inherient the basic infomation from `base_desc`, and modify some fields.
// Inherient the basic information from `base_desc`, and modify some fields.
framework::proto::OpDesc PrepareOpDesc(
const framework::proto::OpDesc& base_desc, const std::string& bias,
const std::string& activation, const std::string& output) {

@ -382,7 +382,7 @@ const VarDesc *FuseOptimizerOpPass::GetVarDescFromVarsInfo(
const std::string &var_name) const {
auto grad_iter = vars_info.find(var_name);
PADDLE_ENFORCE_EQ(grad_iter != vars_info.end(), true,
"The gradient varibale %s is not found.", var_name);
"The gradient variable %s is not found.", var_name);
PADDLE_ENFORCE_EQ(!grad_iter->second.empty(), true,
"The gradient var node %s is not found.", var_name);
PADDLE_ENFORCE_NOT_NULL(grad_iter->second.front()->Var(),

@ -131,7 +131,7 @@ bool GraphPatternDetector::MarkPDNodesInGraph(const ir::Graph &graph) {
}
// The intermediate Nodes can only link to the nodes inside the pattern, or this
// subgraph will be droped.
// subgraph will be dropped.
void GraphPatternDetector::ValidateByNodeRole(
std::vector<GraphPatternDetector::subgraph_t> *subgraphs) {
std::vector<GraphPatternDetector::subgraph_t> result;

@ -179,7 +179,7 @@ void BatchMergePass::ApplyImpl(ir::Graph* graph) const {
ir::Node* var = nullptr;
auto updated_var = UpdateGradVarDesc(in_node->Var(), i, grad_names,
bn_vars_need_rename);
// should be initialized by startup, how to initilize tensor in the
// should be initialized by startup, how to initialize tensor in the
// scope?
if (node->Name() == "batch_norm" &&
bn_vars_need_rename.find(in_node->Name()) !=

@ -1041,7 +1041,7 @@ void DistSSAGraphBuilder::InsertPostprocessOps(ir::Graph *result) const {
// There are 4 conditions:
// 1. GPU && Reduce: Reduce gradient then broadcast gradient to other GPUS.
// Need to broadcast received parameters to other GPU.
// 2. GPU && AllReduce: AllReduce all graident to each GPU. Need to
// 2. GPU && AllReduce: AllReduce all gradient to each GPU. Need to
// broadcast received parameters to other GPU.
// 3. CPU && AllReduce: AllReduce all gradient to each thread. Need to
// broadcast received parameters to other scope.

@ -80,7 +80,7 @@ class CompileTimeInferShapeContext : public InferShapeContext {
PADDLE_ENFORCE_EQ(
in_var_names.size(), out_var_names.size(),
platform::errors::PreconditionNotMet(
"Op [%s]: Input var number shoule be equal with output var number",
"Op [%s]: Input var number should be equal with output var number",
op_.Type()));
for (size_t i = 0; i < in_var_names.size(); ++i) {
@ -663,7 +663,7 @@ void OpDesc::Flush() {
void OpDesc::CheckAttrs() {
PADDLE_ENFORCE(!Type().empty(),
"CheckAttr() can not be called before type is setted.");
"CheckAttr() can not be called before type is set.");
auto *checker = OpInfoMap::Instance().Get(Type()).Checker();
if (checker == nullptr) {
// checker is not configured. That operator could be generated by Paddle,
@ -706,7 +706,7 @@ void OpDesc::InferShape(const BlockDesc &block) const {
void OpDesc::InferVarType(BlockDesc *block) const {
// There are a few places that var type can be set.
// When VarDesc is created, default set to LOD_TENSOR.
// When output variable is created, default is defaut set to LOD_TENSOR.
// When output variable is created, default is default set to LOD_TENSOR.
// We limit here to be the only place that operator defines its customized
// var type inference. Hence, we don't do any "default" setting here.
auto &info = OpInfoMap::Instance().Get(this->Type());

@ -654,7 +654,7 @@ class RuntimeInferShapeContext : public InferShapeContext {
PADDLE_ENFORCE_EQ(
in_var_list.size(), out_var_list.size(),
platform::errors::PreconditionNotMet(
"Op [%s]: Input var size should be equal with ouput var size",
"Op [%s]: Input var size should be equal with output var size",
op_.Type()));
auto& out_var_names = op_.Outputs(out);

@ -53,8 +53,8 @@ constexpr char kEmptyVarName[] = "@EMPTY@";
constexpr char kTempVarName[] = "@TEMP@";
/// If a variable's name has a certain suffix, it means that the
/// variable is the gradient of another varibale.
/// e.g. Variable "x@GRAD" is the gradient of varibale "x".
/// variable is the gradient of another variable.
/// e.g. Variable "x@GRAD" is the gradient of variable "x".
constexpr char kGradVarSuffix[] = "@GRAD";
constexpr size_t kGradVarSuffixSize = 5U;

@ -340,7 +340,7 @@ class IndicateLoDTensorDataTypeTestProtoMaker : public OpProtoAndCheckerMaker {
public:
void Make() {
AddInput("LoDTensor", "Input of Tensor type Variable.");
AddComment("This Op is only for IndicateVarDataType inferface test.");
AddComment("This Op is only for IndicateVarDataType interface test.");
}
};
@ -362,7 +362,7 @@ class IndicateSelectedRowsDataTypeTestProtoMaker
public:
void Make() {
AddInput("SelectedRows", "Input of SelectedRows type Variable.");
AddComment("This Op is only for IndicateVarDataType inferface test.");
AddComment("This Op is only for IndicateVarDataType interface test.");
}
};
@ -382,7 +382,7 @@ class IndicateOtherDataTypeTestProtoMaker : public OpProtoAndCheckerMaker {
public:
void Make() {
AddInput("Other", "Input of Other type Variable");
AddComment("This Op is only for IndicateVarDataType inferface test.");
AddComment("This Op is only for IndicateVarDataType interface test.");
}
};
@ -572,7 +572,7 @@ class GetSetLoDLevelTestMaker : public OpProtoAndCheckerMaker {
void Make() {
AddInput("X", "(LoDTensor) Input Variable.");
AddOutput("Out", "(LoDTensor) Output Variable.");
AddComment("This Op is only for Get/SetLoDLevel inferface test.");
AddComment("This Op is only for Get/SetLoDLevel interface test.");
}
};

@ -112,7 +112,7 @@ void RenameAndGetOutputs(
std::unordered_map<std::string, std::string> *output_name_map,
const std::unordered_map<std::string, framework::ir::Node *> &graph_var_map,
bool trt_and_not_int8) {
//// In the normal case, the paddle-trt exists bug when runing the googlenet.
//// In the normal case, the paddle-trt exists bug when running the googlenet.
// When there are more than two convolutions of 1 * 1 with the same input, the
// paddle-tensorrt will do the merging optimization, which fuse those conv
// into one conv, and then trigger bug. So, We should use strategy to avoid

@ -223,7 +223,7 @@ void TensorRtSubgraphPass::CreateTensorRTOp(
auto use_static_engine = Get<bool>("use_static_engine");
// TODO(NHZlX)
// There are models with the same structure but the different parameters,
// when runing in the 'use_serialize' mode, there is a bug.
// when running in the 'use_serialize' mode, there is a bug.
auto engine_key = GenerateEngineKey(input_names_with_id, output_names_with_id,
std::to_string(0));
auto predictor_id = Get<int>("predictor_id");

@ -137,7 +137,7 @@ std::unique_ptr<framework::ProgramDesc> Load(framework::Executor* executor,
"model version %ld is not supported.",
main_program->Version());
// model_from_memory is false in seperate parameters.
// model_from_memory is false in separate parameters.
LoadPersistables(executor, scope, *main_program, dirname, "",
false /* model_from_memory */);
return main_program;

@ -101,7 +101,7 @@ class TRTConvertValidation {
DeclVar(name, dim_vec);
}
// Declare a parameter varaible in the scope.
// Declare a parameter variable in the scope.
void DeclParamVar(const std::string& name, const nvinfer1::Dims& dims) {
DeclVar(name, dims, true);
}

@ -104,10 +104,9 @@ void TensorRTEngine::FreezeNetwork() {
for (auto &t : all_t) {
if (!quant_dynamic_range_.count(t)) {
VLOG(3)
<< "We are in trt int8 mode(not calibration), scale not setted"
<< " for tensor " << t->getName()
<< ", this might be ok when trt does not need this range";
VLOG(3) << "We are in trt int8 mode(not calibration), scale not set"
<< " for tensor " << t->getName()
<< ", this might be ok when trt does not need this range";
}
}
std::unordered_set<std::string> all_out_t_name;

@ -172,7 +172,7 @@ class ArrayToLoDTensorOpProtoMaker : public framework::OpProtoAndCheckerMaker {
"(std::vector<LodTensor>) A vector of tensors that is going to "
"be casted to a big LoDTensor.");
AddInput("RankTable",
"(LoDRankTable) RankTable provides the coarse lod infomation to "
"(LoDRankTable) RankTable provides the coarse lod information to "
"build the output LoDTensor. See "
"'paddle/framework/lod_rank_table.h' for more details.");
AddOutput("Out", "(LoDTensor) The LoDTensor formed by input tensor array.");

@ -132,7 +132,7 @@ class AverageAccumulatesOpMaker : public framework::OpProtoAndCheckerMaker {
"(Tensor<int64_t>), The accumulating times of previous window with "
"shape [1].");
AddInput("in_num_updates",
"(Tensor<int64_t>), The total number of batches used by trainning "
"(Tensor<int64_t>), The total number of batches used by training "
"before this batch with shape [1].");
AddOutput("out_sum_1",
@ -155,10 +155,9 @@ class AverageAccumulatesOpMaker : public framework::OpProtoAndCheckerMaker {
"out_old_num_accumulates",
"(Tensor<int64_t>) The accumulating times of previous window with "
"shape [1].");
AddOutput(
"out_num_updates",
"(Tensor<int64_t>), The total number of batches used by trainning "
"before this batch with shape [1].");
AddOutput("out_num_updates",
"(Tensor<int64_t>), The total number of batches used by training "
"before this batch with shape [1].");
AddAttr<float>("average_window",
"(float, default 0) "

@ -49,7 +49,7 @@ class BilinearTensorProductKernel : public framework::OpKernel<T> {
auto& place = *ctx.template device_context<DeviceContext>().eigen_device();
auto& dev_ctx = ctx.template device_context<DeviceContext>();
// Create the intermediate variable to caculate the result of
// Create the intermediate variable to calculate the result of
// Input(X) multiplied by Input(Weight_i), the formula is:
// left_mul = X Weight_i.
Tensor left_mul;

@ -267,7 +267,7 @@ void Conv2DTransposeOpMaker::Make() {
"workspace is a section of GPU memory which will be "
"allocated/freed each time the operator runs, larger "
"workspace size can increase performance but also requires "
"better hardward. This size should be carefully setted.")
"better hardward. This size should be carefully set.")
.SetDefault(platform::GetDefaultConvWorkspaceSizeLimitMB());
AddComment(R"DOC(
Convolution2D Transpose Operator.
@ -368,7 +368,7 @@ void Conv3DTransposeOpMaker::Make() {
"workspace is a section of GPU memory which will be "
"allocated/freed each time the operator runs, larger "
"workspace size can increase performance but also requires "
"better hardward. This size should be carefully setted.")
"better hardward. This size should be carefully set.")
.SetDefault(platform::GetDefaultConvWorkspaceSizeLimitMB());
AddComment(R"DOC(
Convolution3D Transpose Operator.

@ -36,7 +36,7 @@ class CropOp : public framework::OperatorWithKernel {
auto shape = ctx->Attrs().Get<std::vector<int>>("shape");
PADDLE_ENFORCE_EQ(
int64_t(shape.size()), x_dim.size(),
"Shape size should be equal to dimention size of input tensor.");
"Shape size should be equal to dimension size of input tensor.");
std::vector<int64_t> tensor_shape(shape.size());
for (size_t i = 0; i < shape.size(); ++i) {
tensor_shape[i] = static_cast<int64_t>(shape[i]);

@ -82,7 +82,7 @@ class CropTensorOp : public framework::OperatorWithKernel {
}
PADDLE_ENFORCE_EQ(int64_t(shape.size()), x_dim.size(),
"Attr(shape)'size of Op(crop_tensor) should be equal to "
"dimention size of input tensor.");
"dimension size of input tensor.");
std::vector<int64_t> out_shape(shape.size(), -1);
for (size_t i = 0; i < shape.size(); ++i) {
if (shape[i] > 0) {

@ -157,7 +157,7 @@ void CropTensorFunction(const framework::ExecutionContext& context) {
// get shape from Input(ShapeTensor) of Input(Shape)
std::vector<int> shape = GetShape(context);
// out_dims setted by arrt(shape)
// out_dims set by arrt(shape)
if (shape.size() == 0) {
for (int i = 0; i < out_dims.size(); ++i) {
shape.push_back(out_dims[i]);

@ -203,7 +203,7 @@ class CrossEntropyOpMaker : public framework::OpProtoAndCheckerMaker {
"represents the cross entropy loss.");
AddAttr<bool>("soft_label",
"(bool, default false), a flag indicating whether to "
"interpretate the given labels as soft labels.")
"interpretant the given labels as soft labels.")
.SetDefault(false);
AddAttr<int>("ignore_index",
"(int, default -100), Specifies a target value that is"

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