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111 lines
4.0 KiB
111 lines
4.0 KiB
/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/fluid/operators/cast_op.h"
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#include "paddle/fluid/platform/float16.h"
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#include "paddle/fluid/platform/gpu_launch_config.h"
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namespace paddle {
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namespace operators {
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// aligned vector generates vectorized load/store on CUDA
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template <typename T, int Size>
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struct alignas(sizeof(T) * Size) AlignedVector {
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T val[Size];
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};
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template <typename T>
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inline int VectorizedSize(const T* pointer) {
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uint64_t address = reinterpret_cast<uint64_t>(pointer);
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constexpr int vec4 = std::alignment_of<AlignedVector<T, 4>>::value; // NOLINT
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if (address % vec4 == 0) {
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return 4;
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}
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return 1;
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}
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template <typename InT, typename OutT, int VecSize>
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__global__ void VecCastCUDAKernel(const InT* in, const int64_t N, OutT* out) {
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int64_t idx = blockDim.x * blockIdx.x + threadIdx.x;
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using LoadT = AlignedVector<InT, VecSize>;
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using StoreT = AlignedVector<OutT, VecSize>;
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for (int i = idx * VecSize; i < N; i += blockDim.x * gridDim.x * VecSize) {
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InT in_vec[VecSize];
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LoadT* in_value = reinterpret_cast<LoadT*>(&in_vec);
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*in_value = *reinterpret_cast<const LoadT*>(&in[i]);
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OutT out_vec[VecSize];
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#pragma unroll
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for (int ii = 0; ii < VecSize; ii++) {
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out_vec[ii] = static_cast<OutT>(in_vec[ii]);
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}
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*(reinterpret_cast<StoreT*>(&out[i])) =
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*reinterpret_cast<StoreT*>(&out_vec[0]);
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}
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}
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template <typename InT, typename OutT>
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__global__ void CastCUDAKernel(const InT* in, const int64_t N, OutT* out) {
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CUDA_KERNEL_LOOP(index, N) { out[index] = static_cast<OutT>(in[index]); }
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}
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template <typename InT>
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struct CastOpFunctor<platform::CUDADeviceContext, InT> {
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const framework::Tensor* in_;
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framework::Tensor* out_;
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const platform::CUDADeviceContext& ctx_;
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CastOpFunctor(const framework::Tensor* in, framework::Tensor* out,
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const platform::CUDADeviceContext& ctx)
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: in_(in), out_(out), ctx_(ctx) {}
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template <typename OutT>
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void apply() const {
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auto* in = in_->data<InT>();
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auto size = in_->numel();
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auto* out = out_->mutable_data<OutT>(ctx_.GetPlace());
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platform::GpuLaunchConfig config =
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platform::GetGpuLaunchConfig1D(ctx_, size);
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int vec_size = VectorizedSize<OutT>(out);
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if (!std::is_same<InT, OutT>::value && vec_size == 4 && size % 4 == 0) {
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VecCastCUDAKernel<InT, OutT, 4><<<
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config.block_per_grid, config.thread_per_block, 0, ctx_.stream()>>>(
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in, size, out);
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} else {
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CastCUDAKernel<InT, OutT><<<config.block_per_grid,
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config.thread_per_block, 0, ctx_.stream()>>>(
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in, size, out);
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}
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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REGISTER_OP_CUDA_KERNEL(
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cast, ops::CastOpKernel<paddle::platform::CUDADeviceContext, float>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext, double>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext, int>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext, int64_t>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext, bool>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext, uint8_t>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext,
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paddle::platform::float16>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext,
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paddle::platform::complex64>,
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ops::CastOpKernel<paddle::platform::CUDADeviceContext,
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paddle::platform::complex128>);
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