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95 lines
3.2 KiB
95 lines
3.2 KiB
/* Copyright (c) 2020 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/fluid/operators/mv_op.h"
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#include "paddle/fluid/platform/gpu_launch_config.h"
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namespace paddle {
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namespace operators {
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template <typename T>
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__global__ void MVGradDxCUDAKernel(const int m, const int n, const T *dout,
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const T *vec, T *dx) {
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int idx = blockDim.x * blockIdx.x + threadIdx.x;
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for (; idx < m * n; idx += blockDim.x * gridDim.x) {
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int i = idx / n;
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int j = idx % n;
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dx[idx] = dout[i] * vec[j];
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}
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}
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// Using dimensional constraints on matrix multiplication, it is
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// straight-forward to check the following table for when X and Y
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// are both matrices.
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//
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// dX = | dOut Vec^T
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// dVec = | X^T dOut
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template <typename T>
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class MVGradKernel<platform::CUDADeviceContext, T>
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: public framework::OpKernel<T> {
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public:
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void Compute(const framework::ExecutionContext &context) const override {
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auto *x = context.Input<framework::Tensor>("X");
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auto *vec = context.Input<framework::Tensor>("Vec");
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auto *dout =
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context.Input<framework::Tensor>(framework::GradVarName("Out"));
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auto *dx = context.Output<framework::Tensor>(framework::GradVarName("X"));
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auto *dvec =
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context.Output<framework::Tensor>(framework::GradVarName("Vec"));
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auto dim_x = x->dims();
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int m = dim_x[0];
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int n = dim_x[1];
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// get data ptr
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const T *x_data = x->data<T>();
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const T *vec_data = vec->data<T>();
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const T *dout_data = dout->data<T>();
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auto &dev_ctx =
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context.template device_context<platform::CUDADeviceContext>();
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auto blas = math::GetBlas<platform::CUDADeviceContext, T>(dev_ctx);
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auto stream = context.cuda_device_context().stream();
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auto config = GetGpuLaunchConfig1D(dev_ctx, m * n);
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if (dx) {
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T *dx_data = dx->mutable_data<T>(context.GetPlace());
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MVGradDxCUDAKernel<
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T><<<config.block_per_grid.x, config.thread_per_block.x, 0, stream>>>(
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m, n, dout_data, vec_data, dx_data);
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}
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if (dvec) {
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T *dvec_data = dvec->mutable_data<T>(context.GetPlace());
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blas.GEMV(true, dim_x[0], dim_x[1], static_cast<T>(1), x_data, dout_data,
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static_cast<T>(0), dvec_data);
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}
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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namespace plat = paddle::platform;
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REGISTER_OP_CUDA_KERNEL(
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mv, ops::MVKernel<paddle::platform::CUDADeviceContext, float>,
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ops::MVKernel<paddle::platform::CUDADeviceContext, double>);
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REGISTER_OP_CUDA_KERNEL(
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mv_grad, ops::MVGradKernel<paddle::platform::CUDADeviceContext, float>,
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ops::MVGradKernel<paddle::platform::CUDADeviceContext, double>);
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