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157 lines
6.4 KiB
157 lines
6.4 KiB
/* Copyright (c) 2016 paddlepaddle Authors. All Rights Reserve.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/operators/math/unpooling.h"
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#include "paddle/platform/cuda_helper.h"
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namespace paddle {
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namespace operators {
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namespace math {
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template <typename T>
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__global__ void KernelUnpool2dMax(const int nthreads,
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const T* input_data,
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const T* indices_data,
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const int input_height,
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const int input_width,
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const int channels,
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T* output_data,
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const int output_height,
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const int output_width) {
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int bsize = input_height * input_width * channels;
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int csize = input_height * input_width;
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int out_bsize = output_height * output_width * channels;
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int out_csize = output_height * output_width;
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int index = blockIdx.x * blockDim.x + threadIdx.x;
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int offset = blockDim.x * gridDim.x;
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for (int i = index; i < nthreads; i += offset) {
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int bidx = i / bsize;
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int boffset = i % bsize;
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int cidx = boffset / csize;
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int out_offset = bidx * out_bsize + cidx * out_csize;
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int out_index = indices_data[i];
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PADDLE_ASSERT(out_index < (output_height * output_width));
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output_data[out_offset + out_index] = input_data[i];
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}
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}
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template <typename T>
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__global__ void KernelUnpool2dMaxGrad(const int nthreads,
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const T* input_data,
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const T* indices_data,
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const int input_height,
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const int input_width,
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const int channels,
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const T* output_data,
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const T* output_grad,
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const int output_height,
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const int output_width,
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T* input_grad) {
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int bsize = input_height * input_width * channels;
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int csize = input_height * input_width;
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int out_bsize = output_height * output_width * channels;
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int out_csize = output_height * output_width;
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int index = blockIdx.x * blockDim.x + threadIdx.x;
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int offset = blockDim.x * gridDim.x;
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for (int i = index; i < nthreads; i += offset) {
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int bidx = i / bsize;
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int boffset = i % bsize;
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int cidx = boffset / csize;
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int out_offset = bidx * out_bsize + cidx * out_csize;
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int out_index = indices_data[i];
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PADDLE_ASSERT(out_index < (output_height * output_width));
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input_grad[i] = output_grad[out_offset + out_index];
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}
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}
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/*
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* All tensors are in NCHW format.
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*/
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template <typename T>
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class Unpool2dMaxFunctor<platform::GPUPlace, T> {
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public:
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void operator()(const platform::DeviceContext& context,
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const framework::Tensor& input,
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const framework::Tensor& indices,
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framework::Tensor * output) {
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const int batch_size = input.dims()[0];
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const int input_height = input.dims()[2];
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const int input_width = input.dims()[3];
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const int output_channels = output->dims()[1];
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const int output_height = output->dims()[2];
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const int output_width = output->dims()[3];
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const T* input_data = input.data<T>();
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const T* indices_data = indices.data<T>();
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T* output_data = output->mutable_data<T>(context.GetPlace());
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int nthreads = batch_size * output_channels * input_height * input_width;
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int blocks = (nthreads + 1024 - 1) / 1024;
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dim3 threads(1024, 1);
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dim3 grid(blocks, 1);
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KernelUnpool2dMax<
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T><<<grid, threads, 0,
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reinterpret_cast<const platform::CUDADeviceContext&>(context)
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.stream()>>>(nthreads, input_data, indices_data,
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input_height, input_width, output_channels,
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output_data, output_height, output_width);
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}
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};
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/*
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* All tensors are in NCHW format.
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*/
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template <typename T>
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class Unpool2dMaxGradFunctor<platform::GPUPlace, T> {
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public:
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void operator()(const platform::DeviceContext& context,
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const framework::Tensor& input,
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const framework::Tensor& indices,
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framework::Tensor * input_grad,
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const framework::Tensor& output,
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const framework::Tensor& output_grad) {
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const int batch_size = input.dims()[0];
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const int input_height = input.dims()[2];
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const int input_width = input.dims()[3];
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const int output_channels = output.dims()[1];
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const int output_height = output.dims()[2];
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const int output_width = output.dims()[3];
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const T* input_data = input.data<T>();
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const T* indices_data = indices.data<T>();
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const T* output_data = output.data<T>();
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const T* output_grad_data = output_grad.data<T>();
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T* input_grad_data = input_grad->mutable_data<T>(context.GetPlace());
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int nthreads = batch_size * output_channels * input_height * input_width;
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int blocks = (nthreads + 1024 - 1) / 1024;
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dim3 threads(1024, 1);
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dim3 grid(blocks, 1);
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KernelUnpool2dMaxGrad<
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T><<<grid, threads, 0,
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reinterpret_cast<const platform::CUDADeviceContext&>(context)
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.stream()>>>(
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nthreads, input_data, indices_data,
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input_height, input_width, output_channels,
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output_data, output_grad_data,
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output_height, output_width,
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input_grad_data);
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}
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};
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template class Unpool2dMaxGradFunctor<platform::GPUPlace, float>;
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template class Unpool2dMaxGradFunctor<platform::GPUPlace, double>;
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template class Unpool2dMaxFunctor<platform::GPUPlace, float>;
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template class Unpool2dMaxFunctor<platform::GPUPlace, double>;
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} // namespace math
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} // namespace operators
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} // namespace paddle
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