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431 lines
19 KiB
431 lines
19 KiB
/* Copyright (c) 2016 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/fluid/operators/conv_transpose_op.h"
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#include <memory>
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#include <string>
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#include <vector>
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#include "paddle/fluid/platform/cudnn_workspace_helper.h"
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#ifdef PADDLE_WITH_MKLDNN
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#include "paddle/fluid/platform/mkldnn_helper.h"
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#endif
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namespace paddle {
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namespace operators {
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void ConvTransposeOp::InferShape(framework::InferShapeContext* ctx) const {
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PADDLE_ENFORCE(ctx->HasInput("Input"),
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"Input(Input) of ConvTransposeOp should not be null.");
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PADDLE_ENFORCE(ctx->HasInput("Filter"),
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"Input(Filter) of ConvTransposeOp should not be null.");
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PADDLE_ENFORCE(ctx->HasOutput("Output"),
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"Output(Output) of ConvTransposeOp should not be null.");
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auto in_dims = ctx->GetInputDim("Input");
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auto filter_dims = ctx->GetInputDim("Filter");
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std::vector<int> output_size =
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ctx->Attrs().Get<std::vector<int>>("output_size");
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std::vector<int> strides = ctx->Attrs().Get<std::vector<int>>("strides");
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std::vector<int> paddings = ctx->Attrs().Get<std::vector<int>>("paddings");
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std::vector<int> dilations = ctx->Attrs().Get<std::vector<int>>("dilations");
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int groups = ctx->Attrs().Get<int>("groups");
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PADDLE_ENFORCE(in_dims.size() == 4 || in_dims.size() == 5,
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"ConvTransposeOp intput should be 4-D or 5-D tensor.");
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PADDLE_ENFORCE_EQ(in_dims.size(), filter_dims.size(),
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"ConvTransposeOp input dimension and filter dimension "
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"should be the same.");
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PADDLE_ENFORCE(in_dims.size() - strides.size() == 2U,
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"ConvTransposeOp input dimension and strides dimension should "
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"be consistent.");
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if (output_size.size())
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PADDLE_ENFORCE_EQ(output_size.size(), strides.size(),
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"ConvTransposeOp output_size dimension and strides "
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"dimension should be the same.");
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PADDLE_ENFORCE_EQ(paddings.size(), strides.size(),
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"ConvTransposeOp paddings dimension and strides "
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"dimension should be the same.");
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PADDLE_ENFORCE_EQ(paddings.size(), dilations.size(),
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"ConvTransposeOp paddings dimension and dilations "
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"dimension should be the same.");
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PADDLE_ENFORCE_EQ(in_dims[1], filter_dims[0],
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"In ConvTransposeOp, The number of input channels should "
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"be equal to the number of filter's channels.");
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std::vector<int64_t> output_shape({in_dims[0], filter_dims[1] * groups});
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for (size_t i = 0; i < strides.size(); ++i) {
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auto filter_extent = dilations[i] * (filter_dims[i + 2] - 1) + 1;
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auto infer_shape =
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(in_dims[i + 2] - 1) * strides[i] - 2 * paddings[i] + filter_extent;
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if (output_size.size()) {
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PADDLE_ENFORCE((output_size[i] >= infer_shape &&
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output_size[i] < infer_shape + strides[i]),
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"ConvTransposeOp output_size should be "
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"in appropriate range.");
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output_shape.push_back(output_size[i]);
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} else {
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output_shape.push_back(infer_shape);
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}
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}
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ctx->SetOutputDim("Output", framework::make_ddim(output_shape));
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}
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framework::OpKernelType ConvTransposeOp::GetExpectedKernelType(
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const framework::ExecutionContext& ctx) const {
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framework::LibraryType library_{framework::LibraryType::kPlain};
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std::string data_format = ctx.Attr<std::string>("data_format");
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framework::DataLayout layout_ = framework::StringToDataLayout(data_format);
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bool use_cudnn = ctx.Attr<bool>("use_cudnn");
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use_cudnn &= platform::is_gpu_place(ctx.GetPlace());
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#ifdef PADDLE_WITH_CUDA
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if (platform::is_gpu_place(ctx.GetPlace())) {
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auto& dev_ctx = ctx.template device_context<platform::CUDADeviceContext>();
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use_cudnn &= dev_ctx.cudnn_handle() != nullptr;
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if (use_cudnn) {
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library_ = framework::LibraryType::kCUDNN;
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}
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}
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#endif
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#ifdef PADDLE_WITH_MKLDNN
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if (library_ == framework::LibraryType::kPlain &&
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platform::CanMKLDNNBeUsed(ctx)) {
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library_ = framework::LibraryType::kMKLDNN;
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layout_ = framework::DataLayout::kMKLDNN;
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}
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#endif
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return framework::OpKernelType(ctx.Input<Tensor>("Input")->type(),
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ctx.GetPlace(), layout_, library_);
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}
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void Conv2DTransposeOpMaker::Make() {
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AddAttr<bool>("is_test",
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"(bool, default false) Set to true for inference only, false "
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"for training. Some layers may run faster when this is true.")
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.SetDefault(false);
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AddInput(
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"Input",
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"(Tensor) The input tensor of convolution transpose operator. "
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"The format of input tensor is NCHW. Where N is batch size, C is the "
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"number of input channels, H is the height of the feature, and "
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"W is the width of the feature.");
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AddInput(
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"Filter",
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"(Tensor) The filter tensor of convolution transpose operator. "
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"The format of the filter tensor is MCHW, where M is the number of "
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"input feature channels, C is the number of "
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"output feature channels,"
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"H is the height of the filter, and W is the width of the filter. "
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"We enforce groups number == 1 in the convolution transpose scenario.");
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AddInput("Bias",
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"(Tensor) Bias to be added to each output of filter application."
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"The format of output tensor is X (one-dimensional) of size equal"
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"to the number of output channels. Only used with MKL-DNN.")
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.AsDispensable();
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AddOutput("Output",
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"(Tensor) The output tensor of convolution transpose operator. "
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"The format of output tensor is also NCHW.");
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AddAttr<std::vector<int>>("output_size",
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"(vector<int> default: []), the "
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"size of the output tensor")
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.SetDefault({});
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AddAttr<int>("groups",
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"(int default:1), the groups number of the convolution "
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"transpose operator. ")
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.SetDefault(1);
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AddAttr<std::vector<int>>("dilations",
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"(vector<int> default:{1, 1}), the "
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"dilations(h_dilation, w_dilation) of convolution "
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"transpose operator.")
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.SetDefault({1, 1});
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AddAttr<std::vector<int>>(
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"strides",
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"(vector<int> default:{1, 1}), the strides(h_stride, w_stride) of "
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"convolution transpose operator.")
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.SetDefault({1, 1});
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AddAttr<std::vector<int>>(
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"paddings",
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"(vector<int> default:{0, 0}), the paddings(h_pad, w_pad) of convolution "
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"transpose operator.")
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.SetDefault({0, 0});
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AddAttr<bool>(
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"use_cudnn",
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"(bool, default false) Only used in cudnn kernel, need install cudnn")
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.SetDefault(false);
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AddAttr<bool>("use_mkldnn",
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"(bool, default false) Only used in mkldnn kernel")
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.SetDefault(false);
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AddAttr<bool>("fuse_relu", "(bool, default false) Only used in mkldnn kernel")
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.SetDefault(false);
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AddAttr<std::string>("fuse_activation",
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"(string, default \"\") Only used in mkldnn kernel")
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.SetDefault("");
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AddAttr<float>("fuse_alpha",
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"(float, default 0.0) Only used in mkldnn kernel")
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.SetDefault(0.0f);
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AddAttr<float>("fuse_beta", "(float, default 0.0) Only used in mkldnn kernel")
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.SetDefault(0.0f);
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AddAttr<std::string>(
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"data_format",
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"(string, default NCHW) Only used in "
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"An optional string from: \"NHWC\", \"NCHW\". "
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"Defaults to \"NHWC\". Specify the data format of the output data, "
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"the input will be transformed automatically. ")
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.SetDefault("AnyLayout");
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// TODO(dzhwinter): need to registered layout transform function
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AddAttr<int>("workspace_size_MB",
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"Used in cudnn kernel only. workspace size for cudnn, in MB, "
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"workspace is a section of GPU memory which will be "
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"allocated/freed each time the operator runs, larger "
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"workspace size can increase performance but also requires "
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"better hardward. This size should be carefully setted.")
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.SetDefault(platform::kDefaultConvWorkspaceSizeLimitMB);
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AddComment(R"DOC(
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Convolution2D Transpose Operator.
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The convolution transpose operation calculates the output based on the input, filter
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and dilations, strides, paddings, groups parameters. The size of each dimension of the
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parameters is checked in the infer-shape.
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Input(Input) and output(Output) are in NCHW format. Where N is batchsize, C is the
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number of channels, H is the height of the feature, and W is the width of the feature.
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Filter(Input) is in MCHW format. Where M is the number of input feature channels,
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C is the number of output feature channels, H is the height of the filter,
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and W is the width of the filter.
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Parameters(strides, paddings) are two elements. These two elements represent height
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and width, respectively.
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The input(X) size and output(Out) size may be different.
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For an example:
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Input:
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Input shape: $(N, C_{in}, H_{in}, W_{in})$
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Filter shape: $(C_{in}, C_{out}, H_f, W_f)$
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Output:
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Output shape: $(N, C_{out}, H_{out}, W_{out})$
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Where
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$$
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H_{out} = (H_{in} - 1) * strides[0] - 2 * paddings[0] + dilations[0] * (H_f - 1) + 1 \\
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W_{out} = (W_{in} - 1) * strides[1] - 2 * paddings[1] + dilations[1] * (W_f - 1) + 1
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$$
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)DOC");
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}
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void Conv3DTransposeOpMaker::Make() {
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AddInput("Input",
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"(Tensor) The input tensor of convolution transpose operator."
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"The format of input tensor is NCDHW. Where N is batch size, C is "
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"the number of channels, D is the depth of the feature, H is the "
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"height of the feature, and "
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"W is the width of the feature.");
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AddInput("Filter",
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"(Tensor) The filter tensor of convolution transpose operator."
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"The format of the filter tensor is MCDHW, where M is the number of "
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"input feature channels, C is the number of "
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"output feature channels, D "
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"is the depth of the filter, H is the height of the filter, and "
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"W is the width of the filter."
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"We enforce groups number == 1 and padding == 0 in "
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"the convolution3d transpose scenario.");
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AddOutput("Output",
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"(Tensor) The output tensor of convolution transpose operator."
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"The format of output tensor is also NCDHW."
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"Where N is batch size, C is "
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"the number of channels, D is the depth of the feature, H is the "
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"height of the feature, and W is the width of the feature.");
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AddAttr<std::vector<int>>("output_size",
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"(vector<int> default: []), the "
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"size of the output tensor")
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.SetDefault({});
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AddAttr<std::vector<int>>(
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"dilations",
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"(vector<int> default:{1, 1, 1}), the "
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"dilations(d_dilation,h_dilation, w_dilation) of convolution "
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"transpose operator.")
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.SetDefault({1, 1, 1});
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AddAttr<std::vector<int>>("strides",
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"(vector<int> default:{1, 1, 1}), the "
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"strides{d_stride, h_stride, w_stride} of "
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"convolution transpose operator.")
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.SetDefault({1, 1, 1});
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AddAttr<std::vector<int>>("paddings",
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"(vector<int> default:{0, 0, 0}), paddings(d_pad, "
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"h_pad, w_pad) of convolution transpose operator.")
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.SetDefault({0, 0, 0});
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AddAttr<int>("groups",
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"(int default:1), the groups number of the convolution3d "
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"transpose operator. ")
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.SetDefault(1);
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AddAttr<bool>(
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"use_cudnn",
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"(bool, default false) Only used in cudnn kernel, need install cudnn")
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.SetDefault(false);
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AddAttr<bool>("use_mkldnn",
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"(bool, default false) Only used in mkldnn kernel")
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.SetDefault(false);
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AddAttr<std::string>(
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"data_format",
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"(string, default NCHW) Only used in "
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"An optional string from: \"NHWC\", \"NCHW\". "
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"Defaults to \"NHWC\". Specify the data format of the output data, "
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"the input will be transformed automatically. ")
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.SetDefault("AnyLayout");
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// TODO(dzhwinter): need to registered layout transform function
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AddAttr<int>("workspace_size_MB",
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"Used in cudnn kernel only. workspace size for cudnn, in MB, "
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"workspace is a section of GPU memory which will be "
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"allocated/freed each time the operator runs, larger "
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"workspace size can increase performance but also requires "
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"better hardward. This size should be carefully setted.")
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.SetDefault(platform::kDefaultConvWorkspaceSizeLimitMB);
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AddComment(R"DOC(
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Convolution3D Transpose Operator.
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The convolution transpose operation calculates the output based on the input, filter
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and dilations, strides, paddings, groups parameters. The size of each dimension of the
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parameters is checked in the infer-shape.
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Input(Input) and output(Output) are in NCDHW format. Where N is batch size, C is the
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number of channels, D is the depth of the feature, H is the height of the feature,
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and W is the width of the feature.
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Filter(Input) is in MCDHW format. Where M is the number of input feature channels,
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C is the number of output feature channels, D is the depth of the filter,H is the
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height of the filter, and W is the width of the filter.
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Parameters(strides, paddings) are three elements. These three elements represent
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depth, height and width, respectively.
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The input(X) size and output(Out) size may be different.
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Example:
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Input:
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Input shape: $(N, C_{in}, D_{in}, H_{in}, W_{in})$
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Filter shape: $(C_{in}, C_{out}, D_f, H_f, W_f)$
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Output:
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Output shape: $(N, C_{out}, D_{out}, H_{out}, W_{out})$
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Where
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$$
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D_{out} = (D_{in} - 1) * strides[0] - 2 * paddings[0] + dilations[0] * (D_f - 1) + 1 \\
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H_{out} = (H_{in} - 1) * strides[1] - 2 * paddings[1] + dilations[1] * (H_f - 1) + 1 \\
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W_{out} = (W_{in} - 1) * strides[2] - 2 * paddings[2] + dilations[2] * (W_f - 1) + 1
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$$
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)DOC");
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}
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void ConvTransposeOpGrad::InferShape(framework::InferShapeContext* ctx) const {
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auto in_dims = ctx->GetInputDim("Input");
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auto filter_dims = ctx->GetInputDim("Filter");
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if (ctx->HasOutput(framework::GradVarName("Input"))) {
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ctx->SetOutputDim(framework::GradVarName("Input"), in_dims);
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}
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if (ctx->HasOutput(framework::GradVarName("Filter"))) {
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ctx->SetOutputDim(framework::GradVarName("Filter"), filter_dims);
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}
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}
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framework::OpKernelType ConvTransposeOpGrad::GetExpectedKernelType(
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const framework::ExecutionContext& ctx) const {
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bool use_cudnn = ctx.Attr<bool>("use_cudnn");
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use_cudnn &= platform::is_gpu_place(ctx.GetPlace());
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#ifdef PADDLE_WITH_CUDA
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if (platform::is_gpu_place(ctx.GetPlace())) {
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auto& dev_ctx = ctx.template device_context<platform::CUDADeviceContext>();
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use_cudnn &= dev_ctx.cudnn_handle() != nullptr;
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}
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#endif
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framework::LibraryType library_;
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if (use_cudnn) {
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library_ = framework::LibraryType::kCUDNN;
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} else {
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library_ = framework::LibraryType::kPlain;
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}
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std::string data_format = ctx.Attr<std::string>("data_format");
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framework::DataLayout layout_ = framework::StringToDataLayout(data_format);
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return framework::OpKernelType(ctx.Input<Tensor>("Input")->type(),
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ctx.GetPlace(), layout_, library_);
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}
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class ConvTransposeGradOpDescMaker : public framework::SingleGradOpDescMaker {
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public:
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using framework::SingleGradOpDescMaker::SingleGradOpDescMaker;
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protected:
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std::unique_ptr<framework::OpDesc> Apply() const override {
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std::unique_ptr<framework::OpDesc> op(new framework::OpDesc());
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op->SetType(ForwardOp().Type() + "_grad");
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op->SetInput("Input", Input("Input"));
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op->SetInput("Filter", Input("Filter"));
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op->SetOutput(framework::GradVarName("Input"), InputGrad("Input"));
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op->SetOutput(framework::GradVarName("Filter"), InputGrad("Filter"));
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if (ForwardOp().Inputs().count("Bias") > 0) {
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op->SetInput("Bias", Input("Bias"));
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op->SetOutput(framework::GradVarName("Bias"), InputGrad("Bias"));
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}
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op->SetInput(framework::GradVarName("Output"), OutputGrad("Output"));
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op->SetAttrMap(Attrs());
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return op;
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}
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};
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} // namespace operators
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} // namespace paddle
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namespace ops = paddle::operators;
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// conv2d_transpose
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REGISTER_OPERATOR(conv2d_transpose, ops::ConvTransposeOp,
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ops::Conv2DTransposeOpMaker,
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ops::ConvTransposeGradOpDescMaker);
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REGISTER_OPERATOR(conv2d_transpose_grad, ops::ConvTransposeOpGrad);
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REGISTER_OP_CPU_KERNEL(
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conv2d_transpose,
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ops::GemmConvTransposeKernel<paddle::platform::CPUDeviceContext, float>,
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ops::GemmConvTransposeKernel<paddle::platform::CPUDeviceContext, double>);
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REGISTER_OP_CPU_KERNEL(
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conv2d_transpose_grad,
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ops::GemmConvTransposeGradKernel<paddle::platform::CPUDeviceContext, float>,
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ops::GemmConvTransposeGradKernel<paddle::platform::CPUDeviceContext,
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double>);
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// conv3d_transpose
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REGISTER_OPERATOR(conv3d_transpose, ops::ConvTransposeOp,
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ops::Conv3DTransposeOpMaker,
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ops::ConvTransposeGradOpDescMaker);
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REGISTER_OPERATOR(conv3d_transpose_grad, ops::ConvTransposeOpGrad);
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REGISTER_OP_CPU_KERNEL(
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conv3d_transpose,
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ops::GemmConvTransposeKernel<paddle::platform::CPUDeviceContext, float>,
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ops::GemmConvTransposeKernel<paddle::platform::CPUDeviceContext, double>);
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REGISTER_OP_CPU_KERNEL(
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conv3d_transpose_grad,
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ops::GemmConvTransposeGradKernel<paddle::platform::CPUDeviceContext, float>,
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ops::GemmConvTransposeGradKernel<paddle::platform::CPUDeviceContext,
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double>);
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// depthwise conv2d_transpose
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REGISTER_OPERATOR(depthwise_conv2d_transpose, ops::ConvTransposeOp,
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ops::Conv2DTransposeOpMaker,
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ops::ConvTransposeGradOpDescMaker);
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REGISTER_OPERATOR(depthwise_conv2d_transpose_grad, ops::ConvTransposeOpGrad);
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|
|
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REGISTER_OP_CPU_KERNEL(
|
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depthwise_conv2d_transpose,
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ops::GemmConvTransposeKernel<paddle::platform::CPUDeviceContext, float>,
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ops::GemmConvTransposeKernel<paddle::platform::CPUDeviceContext, double>);
|
|
REGISTER_OP_CPU_KERNEL(
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|
depthwise_conv2d_transpose_grad,
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|
ops::GemmConvTransposeGradKernel<paddle::platform::CPUDeviceContext, float>,
|
|
ops::GemmConvTransposeGradKernel<paddle::platform::CPUDeviceContext,
|
|
double>);
|