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143 lines
3.4 KiB
143 lines
3.4 KiB
/**
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* Copyright 2019-2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef PLATFORM_INFO_DEF_H
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#define PLATFORM_INFO_DEF_H
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#include <map>
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#include <string>
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#include <vector>
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using std::map;
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using std::string;
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using std::vector;
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namespace fe {
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enum MemoryType { DDR = 0, HBM };
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enum L2Type { Cache = 0, Buff };
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typedef struct tag_str_info {
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string aic_version;
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string ccec_aic_version;
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string ccec_aiv_version;
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string is_support_ai_cpu_compiler;
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} StrInfo;
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typedef struct tag_so_c_info {
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uint32_t ai_core_cnt;
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uint32_t vector_core_cnt;
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uint32_t ai_cpu_cnt;
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MemoryType memory_type;
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uint64_t memory_size;
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L2Type l2_type;
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uint64_t l2_size;
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uint32_t l2PageNum;
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} SoCInfo;
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typedef struct tag_ai_core_spec {
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double cube_freq;
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uint64_t cube_m_size;
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uint64_t cube_n_size;
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uint64_t cube_k_size;
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uint64_t vec_calc_size;
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uint64_t l0_a_size;
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uint64_t l0_b_size;
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uint64_t l0_c_size;
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uint64_t l1_size;
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uint64_t smask_buffer;
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uint64_t ub_size;
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uint64_t ubblock_size;
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uint64_t ubbank_size;
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uint64_t ubbank_num;
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uint64_t ubburst_in_one_block;
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uint64_t ubbank_group_num;
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uint32_t unzip_engines;
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uint32_t unzip_max_ratios;
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uint32_t unzip_channels;
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uint8_t unzip_is_tight;
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uint8_t cube_vector_split;
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} AiCoreSpec;
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typedef struct tag_ai_core_memory_rates {
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double ddr_rate;
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double ddr_read_rate;
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double ddr_write_rate;
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double l2_rate;
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double l2_read_rate;
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double l2_write_rate;
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double l1_to_l0_a_rate;
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double l1_to_l0_b_rate;
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double l1_to_ub_rate;
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double l0_c_to_ub_rate;
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double ub_to_l2_rate;
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double ub_to_ddr_rate;
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double ub_to_l1_rate;
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} AiCoreMemoryRates;
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typedef struct tag_vector_core_spec {
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double vec_freq;
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uint64_t vec_calc_size;
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uint64_t smask_buffer;
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uint64_t ub_size;
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uint64_t ubblock_size;
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uint64_t ubbank_size;
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uint64_t ubbank_num;
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uint64_t ubburst_in_one_block;
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uint64_t ubbank_group_num;
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uint64_t vector_reg_size;
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uint64_t predicate_reg_size;
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uint64_t address_reg_size;
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uint64_t alignment_reg_size;
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} VectorCoreSpec;
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typedef struct tag_vector_core_memory_rates {
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double ddr_rate;
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double ddr_read_rate;
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double ddr_write_rate;
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double l2_rate;
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double l2_read_rate;
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double l2_write_rate;
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double ub_to_l2_rate;
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double ub_to_ddr_rate;
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} VectorCoreMemoryRates;
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typedef struct tag_cpu_cache {
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uint32_t AICPUSyncBySW;
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uint32_t TSCPUSyncBySW;
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} CPUCache;
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typedef struct tag_platform_info {
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StrInfo str_info;
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SoCInfo soc_info;
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AiCoreSpec ai_core_spec;
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AiCoreMemoryRates ai_core_memory_rates;
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map<string, vector<string>> ai_core_intrinsic_dtype_map;
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VectorCoreSpec vector_core_spec;
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VectorCoreMemoryRates vector_core_memory_rates;
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CPUCache cpucache;
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map<string, vector<string>> vector_core_intrinsic_dtype_map;
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} PlatformInfo;
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typedef struct tag_optional_info {
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string soc_version;
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string core_type;
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uint32_t ai_core_num;
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string l1_fusion_flag;
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} OptionalInfo;
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} // namespace fe
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#endif
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