!6202 [MSLITE][Develop] arm cpu int8 conv depthwise support arm32
Merge pull request !6202 from yangruoqi713/int8_arm32pull/6202/MERGE
mindspore-ci-bot
4 years ago
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commit
07422d5438
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#ifdef __arm__
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#ifndef __aarch64__
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.text
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.align 5
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.global ConvDwInt8PostAlign4
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#ifndef __APPLE__
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.type ConvDwInt8PostAlign4, %function
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#endif
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// void ConvDwInt8PostAlign4(int8_t *dst, int32_t *buffer, int num_pixels, int32_t output_zp, int32_t out_multiplier,
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// int32_t left_shift, int32_t right_shift, int32_t acc_min, int32_t acc_max);
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// r0: dst, r1: buffer, r2: num_pixels, r3: output_zp, r4: out_multiplier,
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// r5: left_shift, r6: right_shift, r7: acc_min, r8: acc_max
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ConvDwInt8PostAlign4:
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// at return, clang generates "push {lr}, pop {pc}"" while gcc will generate "bx lr"
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// according to https://stackoverflow.com/questions/53625807
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// even if we jump to link register instead of saving it, we still have to save it in subroutine calls anyway
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// clang's rule seems more simple, though there are no subroutine calls here
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// r4-r8 and q4-q7 must be saved according to https://static.docs.arm.com/ihi0042/i/aapcs32.pdf
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push {r4-r8, r10}
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vpush {q4-q7}
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add sp, sp, #88
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vdup.32 q15, r3 // output_zp
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ldr r4, [sp] // out_multiplier
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vdup.32 q14, r4
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ldr r5, [sp, #4] // left_shift
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vdup.32 q13, r5
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ldr r6, [sp, #8] // right_shift
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vdup.32 q12, r6
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ldr r7, [sp, #12] // acc_min
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vdup.32 q11, r7
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ldr r8, [sp, #16] // acc_max
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vdup.32 q10, r8
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mov r10, r0
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LoopDepth8:
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cmp r2, #8
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blt End
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vld1.32 {q0}, [r1]!
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vshl.s32 q0, q0, q13
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vqrdmulh.s32 q0, q0, q14
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vand q4, q0, q12
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vshr.s32 q4, q4, #31
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vqadd.s32 q0, q0, q4
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vrshl.s32 q0, q0, q12
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vadd.i32 q0, q0, q15
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vmax.s32 q0, q0, q11
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vmin.s32 q0, q0, q10
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vqmovn.s32 d4, q0
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vld1.32 {q1}, [r1]!
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vshl.s32 q1, q1, q13
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vqrdmulh.s32 q1, q1, q14
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vand q4, q1, q12
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vshr.s32 q4, q4, #31
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vqadd.s32 q1, q1, q4
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vrshl.s32 q1, q1, q12
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vadd.i32 q1, q1, q15
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vmax.s32 q1, q1, q11
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vmin.s32 q1, q1, q10
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vqmovn.s32 d5, q1
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vqmovn.s16 d4, q2
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vst1.8 {d4}, [r10]!
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sub r2, r2, #8
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b LoopDepth8
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LoopDepth4:
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cmp r2, #4
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blt End
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vld1.32 {q0}, [r1]!
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vshl.s32 q0, q0, q13
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vqrdmulh.s32 q0, q0, q14
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vand q4, q0, q12
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vshr.s32 q4, q4, #31
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vqadd.s32 q0, q0, q4
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vrshl.s32 q0, q0, q12
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vadd.i32 q0, q0, q15
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vmax.s32 q0, q0, q11
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vmin.s32 q0, q0, q10
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vqmovn.s32 d0, q0
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vqmovn.s16 d0, q0
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vst1.8 {d0[0]}, [r10]!
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vst1.8 {d0[1]}, [r10]!
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vst1.8 {d0[2]}, [r10]!
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vst1.8 {d0[3]}, [r10]!
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sub r2, r2, #4
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b LoopDepth4
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End:
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sub sp, sp, #88
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vpop {q4-q7}
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pop {r4-r8, r10}
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bx lr
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#endif
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#endif
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@ -0,0 +1,134 @@
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#ifdef __arm__
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#ifndef __aarch64__
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.text
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.align 5
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.global ConvDwInt8Row
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#ifndef __APPLE__
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.type ConvDwInt8Row, %function
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#endif
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// void ConvDwInt8Row(int32_t *output_ptr, const int8_t *input_ptr, const int16_t *weight_ptr, int num_pixels,
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// int output_channel, int input_step, int8_t input_zp)
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// r0: output_ptr, r1: input_ptr, r2: weight_ptr, r3: num_pixels,
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// r4: output_channel, r5: input_step, r6: input_zp,
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ConvDwInt8Row:
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// at return, clang generates "push {lr}, pop {pc}"" while gcc will generate "bx lr"
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// according to https://stackoverflow.com/questions/53625807
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// even if we jump to link register instead of saving it, we still have to save it in subroutine calls anyway
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// clang's rule seems more simple, though there are no subroutine calls here
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// r4-r8 and q4-q7 must be saved according to https://static.docs.arm.com/ihi0042/i/aapcs32.pdf
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push {r4-r8, r9-r12, lr}
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vpush {q4-q7}
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add sp, sp, #104
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cmp r3, #0
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beq End
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ldr r4, [sp] // channel
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ldr r5, [sp, #4] // input_step
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ldr r6, [sp, #8] // input_zp
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vdup.8 d30, r6
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mov r7, r0
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LoopPixel:
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mov r8, r1 // input
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mov r10, r2 // weight
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mov r11, r4
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LoopDepth16In:
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cmp r11, #16
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blt L8
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sub r11, r11, #16
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vld1.8 {q0}, [r8]!
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vld1.16 {q1, q2}, [r10]! // weight
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vsubl.s8 q3, d0, d30 // -zp
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vld1.32 {q4, q5}, [r0]!
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vmlal.s16 q4, d6, d2
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vmlal.s16 q5, d7, d3
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cmp r11, #16
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blt LoopDepth16Out
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LoopDepth16:
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vst1.32 {q4, q5}, [r7]!
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vsubl.s8 q6, d1, d30
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vld1.32 {q7, q8}, [r0]!
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vmlal.s16 q7, d12, d4
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vmlal.s16 q8, d13, d5
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vst1.32 {q7, q8}, [r7]!
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vld1.8 {q0}, [r8]!
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vld1.16 {q1, q2}, [r10]! // weight
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vsubl.s8 q3, d0, d30 // -zp
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vld1.32 {q4, q5}, [r0]!
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vmlal.s16 q4, d6, d2
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vmlal.s16 q5, d7, d3
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sub r11, r11, #16
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cmp r11, #16
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bge LoopDepth16
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LoopDepth16Out:
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vst1.32 {q4, q5}, [r7]!
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vsubl.s8 q6, d1, d30
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vld1.32 {q7, q8}, [r0]!
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vmlal.s16 q7, d12, d4
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vmlal.s16 q8, d13, d5
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vst1.32 {q7, q8}, [r7]!
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L8:
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cmp r11, #8
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blt L0
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LoopDepth8:
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vld1.8 {d0}, [r8]!
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vld1.16 {d2, d3}, [r10]! // weight
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vsubl.s8 q2, d0, d30 // -zp
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vld1.32 {q3}, [r0]!
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vmlal.s16 q3, d4, d2
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vst1.32 {q3}, [r7]!
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vld1.32 {q4}, [r0]!
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vmlal.s16 q4, d5, d3
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vst1.32 {q4}, [r7]!
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sub r11, r11, #8
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cmp r11, #8
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bge LoopDepth8
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L0:
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cmp r11, #0
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beq LoopDepthEnd
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LoopDepth0:
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ldrsb r12, [r8], #1
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ldrsh r9, [r10], #2
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sub r12, r12, r6
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ldr lr, [r0], #4
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smlabb r12, r12, r9, lr
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str r12, [r7], #4
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subs r11, r11, #1
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bne L0
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LoopDepthEnd:
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add r1, r1, r5
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subs r3, r3, #1
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bne LoopPixel
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End:
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sub sp, sp, #104
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vpop {q4-q7}
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pop {r4-r8, r9-r12, pc}
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#endif
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#endif
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