!12152 Rewrite sequence_mask as a composite op
From: @TFbunny Reviewed-by: @robingrosman Signed-off-by:pull/12152/MERGE
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adf934c567
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <cstdint>
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#include "backend/kernel_compiler/gpu/arrays/sequence_mask_gpu_kernel.h"
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namespace mindspore {
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namespace kernel {
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// keep this as TWO but output is always bool, just in case framework can
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// support passing optional dtype and then we can be identical to tf
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MS_REG_GPU_KERNEL_TWO(
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SequenceMask,
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KernelAttr().AddInputAttr(kNumberTypeInt32).AddInputAttr(kNumberTypeInt32).AddOutputAttr(kNumberTypeBool),
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SequenceMaskGpuKernel, int32_t, bool)
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MS_REG_GPU_KERNEL_TWO(
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SequenceMask,
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KernelAttr().AddInputAttr(kNumberTypeInt64).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeBool),
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SequenceMaskGpuKernel, int64_t, bool)
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} // namespace kernel
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} // namespace mindspore
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_SEQUENCE_MASK_GPU_KERNEL_H_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_SEQUENCE_MASK_GPU_KERNEL_H_
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#include "backend/kernel_compiler/gpu/cuda_impl/sequence_mask_impl.cuh"
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#include <cuda_runtime.h>
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#include <vector>
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#include "backend/kernel_compiler/gpu/gpu_kernel.h"
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#include "backend/kernel_compiler/gpu/gpu_kernel_factory.h"
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namespace mindspore {
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namespace kernel {
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template <typename T, typename S>
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class SequenceMaskGpuKernel : public GpuKernel {
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public:
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SequenceMaskGpuKernel() { ResetResource(); }
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~SequenceMaskGpuKernel() = default;
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const std::vector<size_t> &GetInputSizeList() const override { return input_size_list_; }
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const std::vector<size_t> &GetOutputSizeList() const override { return output_size_list_; }
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const std::vector<size_t> &GetWorkspaceSizeList() const override { return workspace_size_list_; }
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bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
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const std::vector<AddressPtr> &outputs, void *stream_ptr) override {
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T *lengths_device_address = GetDeviceAddress<T>(inputs, 0);
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T *maxlen_device_address = GetDeviceAddress<T>(inputs, 1);
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S *output_device_address = GetDeviceAddress<S>(outputs, 0);
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CalSequenceMask(lengths_device_address, maxlen_device_address, output_device_address, output_size_,
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reinterpret_cast<cudaStream_t>(stream_ptr));
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return true;
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}
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bool Init(const CNodePtr &kernel_node) override {
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size_t input_count = AnfAlgo::GetInputTensorNum(kernel_node);
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if (input_count != 2) {
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MS_LOG(EXCEPTION) << input_count << " inputs were provided, but SequenceMaskGpuKernel expects 2.";
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}
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input_shape_ = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
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for (const int &e : input_shape_) {
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lengths_size_ *= e;
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}
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std::vector<size_t> inferred_output_shape = AnfAlgo::GetOutputInferShape(kernel_node, 0);
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for (const size_t &e : inferred_output_shape) {
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output_size_ *= e;
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}
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InitSizeLists();
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return true;
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}
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void ResetResource() noexcept override {
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output_size_ = 1;
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lengths_size_ = 1;
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input_size_list_.clear();
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output_size_list_.clear();
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workspace_size_list_.clear();
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}
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protected:
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void InitSizeLists() override {
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input_size_list_.push_back(lengths_size_ * sizeof(T));
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input_size_list_.push_back(sizeof(T));
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output_size_list_.push_back(output_size_);
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}
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private:
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std::vector<size_t> input_shape_;
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size_t lengths_size_;
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size_t output_size_;
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std::vector<size_t> input_size_list_;
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std::vector<size_t> output_size_list_;
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std::vector<size_t> workspace_size_list_;
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};
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} // namespace kernel
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} // namespace mindspore
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#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_SEQUENCE_MASK_GPU_KERNEL_H_
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@ -1,50 +0,0 @@
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <cuda_runtime.h>
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#include "sequence_mask_impl.cuh"
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#include "runtime/device/gpu/cuda_common.h"
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__global__ void ValidateArgs(int *maxlen, const int lengths_size, const int max_output_size) {
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int maxlen_value = *maxlen;
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if (maxlen_value < 0 || lengths_size * maxlen_value > max_output_size) {
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asm("trap;");
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}
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}
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template <typename T, typename S>
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__global__ void SequenceMask(
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const T *input, T *maxlen, S *output, const size_t output_size) {
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T maxlen_value = *maxlen;
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for (size_t gt_id = blockIdx.x * blockDim.x + threadIdx.x; gt_id < output_size; gt_id += gridDim.x * blockDim.x) {
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T mask_comparison_value = gt_id % maxlen_value;
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T input_comparison_index = (gt_id - mask_comparison_value) / maxlen_value;
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S result = mask_comparison_value < input[input_comparison_index];
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output[gt_id] = result;
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}
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}
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template <typename T, typename S>
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void CalSequenceMask(const T *lengths, T *maxlen, S *output, const size_t output_size, cudaStream_t cuda_stream) {
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SequenceMask<<<GET_BLOCKS(output_size), GET_THREADS, 0, cuda_stream>>>(lengths, maxlen, output, output_size);
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}
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template void CalSequenceMask<int, bool>(const int *lengths, int *maxlen, bool *output, const size_t output_size,
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cudaStream_t cuda_stream);
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template void CalSequenceMask<int64_t, bool>(const int64_t *lengths, int64_t *maxlen, bool *output,
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const size_t output_size, cudaStream_t cuda_stream);
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@ -1,25 +0,0 @@
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_CUDA_IMPL_SEQUENCE_MASK_CUH_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_CUDA_IMPL_SEQUENCE_MASK_CUH_
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#include <cuda_runtime.h>
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template <typename T, typename S>
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void CalSequenceMask(const T *lengths, T *maxlen, S *output, const size_t output_size, cudaStream_t cuda_stream);
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#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_CUDA_IMPL_SEQUENCE_MASK_CUH_
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