Merge pull request #14440 from hjchen2/develop
Add PRelu tensorRT plugin and Conv2d transpose op converterpanyx0718-patch-1
Zhaolong Xing
6 years ago
committed by
GitHub
commit
2f27c048cc
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/* Copyright (c) 2018 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include "paddle/fluid/inference/tensorrt/convert/op_converter.h"
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#include "paddle/fluid/inference/tensorrt/plugin/prelu_op_plugin.h"
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namespace paddle {
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namespace inference {
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namespace tensorrt {
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/*
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* PRelu converter from fluid to tensorRT.
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*/
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class PReluOpConverter : public OpConverter {
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public:
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void operator()(const framework::proto::OpDesc& op,
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const framework::Scope& scope, bool test_mode) override {
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VLOG(4) << "convert fluid prelu op to tensorrt prelu layer";
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framework::OpDesc op_desc(op, nullptr);
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// Declare inputs
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int input_num = op_desc.Input("X").size();
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PADDLE_ENFORCE(input_num == 1);
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auto* input = engine_->GetITensor(op_desc.Input("X")[0]);
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// Get output
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size_t output_num = op_desc.Output("Out").size();
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PADDLE_ENFORCE(output_num == 1);
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// Get attrs
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std::string mode = boost::get<std::string>(op_desc.GetAttr("mode"));
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//
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auto* alpha_var = scope.FindVar(op_desc.Input("Alpha")[0]);
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PADDLE_ENFORCE_NOT_NULL(alpha_var);
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auto* alpha_tensor = alpha_var->GetMutable<framework::LoDTensor>();
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platform::CUDAPlace place;
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std::unique_ptr<framework::LoDTensor> alpha_tensor_device(
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new framework::LoDTensor());
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alpha_tensor_device->Resize(alpha_tensor->dims());
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TensorCopySync(*alpha_tensor, place, alpha_tensor_device.get());
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float* alpha_data = alpha_tensor_device->mutable_data<float>(place);
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// Transform alpha to TensorRTEngine::Weight
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TensorRTEngine::Weight alpha_rt(nvinfer1::DataType::kFLOAT,
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static_cast<void*>(alpha_data),
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alpha_tensor_device->numel());
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PReluPlugin* plugin = new PReluPlugin(alpha_rt, mode);
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nvinfer1::IPluginLayer* layer =
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engine_->AddPlugin(&input, input_num, plugin);
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// keep alpha tensor to avoid release it's memory
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engine_->weight_map[op_desc.Input("Alpha")[0]] =
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std::move(alpha_tensor_device);
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std::string layer_name = "prelu (Output: ";
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auto output_name = op_desc.Output("Out")[0];
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layer->getOutput(0)->setName(output_name.c_str());
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engine_->SetITensor(output_name, layer->getOutput(0));
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layer_name += output_name;
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if (test_mode) {
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engine_->DeclareOutput(output_name);
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}
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layer->setName((layer_name + ")").c_str());
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}
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};
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} // namespace tensorrt
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} // namespace inference
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} // namespace paddle
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REGISTER_TRT_OP_CONVERTER(prelu, PReluOpConverter);
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/* Copyright (c) 2018 PaddlePaddle Authors. All Rights Reserved.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License. */
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#include <gtest/gtest.h>
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#include "paddle/fluid/inference/tensorrt/convert/op_converter.h"
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#include "paddle/fluid/inference/tensorrt/convert/ut_helper.h"
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namespace paddle {
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namespace inference {
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namespace tensorrt {
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TEST(prelu_op, test_channel_wise) {
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std::unordered_set<std::string> parameters({"prelu_alpha"});
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framework::Scope scope;
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TRTConvertValidation validator(10, parameters, scope, 1000);
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validator.DeclInputVar("prelu_input", nvinfer1::DimsCHW(3, 2, 2));
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validator.DeclParamVar("prelu_alpha", nvinfer1::Dims3(3, 1, 1));
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validator.DeclOutputVar("prelu_out", nvinfer1::DimsCHW(3, 2, 2));
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// Prepare Op description
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framework::OpDesc desc;
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desc.SetType("prelu");
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desc.SetInput("X", {"prelu_input"});
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desc.SetInput("Alpha", {"prelu_alpha"});
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desc.SetOutput("Out", {"prelu_out"});
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desc.SetAttr("mode", std::string("channel"));
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validator.SetOp(*desc.Proto());
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validator.Execute(1);
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}
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TEST(prelu_op, test_element_wise) {
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std::unordered_set<std::string> parameters({"prelu_alpha"});
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framework::Scope scope;
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TRTConvertValidation validator(10, parameters, scope, 1000);
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validator.DeclInputVar("prelu_input", nvinfer1::DimsCHW(3, 2, 2));
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validator.DeclParamVar("prelu_alpha", nvinfer1::Dims4(10, 3, 2, 2));
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validator.DeclOutputVar("prelu_out", nvinfer1::DimsCHW(3, 2, 2));
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// Prepare Op description
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framework::OpDesc desc;
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desc.SetType("prelu");
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desc.SetInput("X", {"prelu_input"});
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desc.SetInput("Alpha", {"prelu_alpha"});
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desc.SetOutput("Out", {"prelu_out"});
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desc.SetAttr("mode", std::string("element"));
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validator.SetOp(*desc.Proto());
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validator.Execute(1);
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}
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TEST(prelu_op, test_scalar) {
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std::unordered_set<std::string> parameters({"prelu_alpha"});
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framework::Scope scope;
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TRTConvertValidation validator(10, parameters, scope, 1000);
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validator.DeclInputVar("prelu_input", nvinfer1::DimsCHW(3, 2, 2));
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validator.DeclParamVar("prelu_alpha", nvinfer1::Dims3(1, 1, 1));
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validator.DeclOutputVar("prelu_out", nvinfer1::DimsCHW(3, 2, 2));
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// Prepare Op description
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framework::OpDesc desc;
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desc.SetType("prelu");
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desc.SetInput("X", {"prelu_input"});
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desc.SetInput("Alpha", {"prelu_alpha"});
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desc.SetOutput("Out", {"prelu_out"});
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desc.SetAttr("mode", std::string("all"));
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validator.SetOp(*desc.Proto());
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validator.Execute(1);
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}
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} // namespace tensorrt
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} // namespace inference
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} // namespace paddle
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// USE_OP(prelu);
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USE_CPU_ONLY_OP(prelu);
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@ -1 +1 @@
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nv_library(tensorrt_plugin SRCS trt_plugin.cc split_op_plugin.cu DEPS enforce)
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nv_library(tensorrt_plugin SRCS trt_plugin.cc split_op_plugin.cu prelu_op_plugin.cu DEPS enforce)
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// Copyright (c) 2018 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <cassert>
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#include "glog/logging.h"
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#include "paddle/fluid/inference/tensorrt/plugin/prelu_op_plugin.h"
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namespace paddle {
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namespace inference {
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namespace tensorrt {
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static const int CUDA_NUM_THREADS = 1024;
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static const int CUDA_MAX_NUM_BLOCKS = 65535;
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inline static int GET_NUM_BLOCKS(const int N) {
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return (N + CUDA_NUM_THREADS - 1) / CUDA_NUM_THREADS;
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}
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__global__ void PReluChannelWiseKernel(const float *input, const float *alpha,
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float *output, int channel,
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size_t spatial_size) {
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size_t offset = blockIdx.x * spatial_size;
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const float *in = input + offset;
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float *out = output + offset;
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float scale = alpha[blockIdx.x % channel];
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for (size_t i = threadIdx.x; i < spatial_size; i += blockDim.x) {
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float x = in[i];
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out[i] = (x > 0) ? x : scale * x;
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}
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}
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__global__ void PReluElementWiseKernel(const float *input, const float *alpha,
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float *output, size_t spatial_size) {
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size_t offset = blockIdx.x * spatial_size;
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const float *in = input + offset;
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const float *scale = alpha + offset;
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float *out = output + offset;
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for (size_t i = threadIdx.x; i < spatial_size; i += blockDim.x) {
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float x = in[i];
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out[i] = (x > 0) ? x : scale[i] * x;
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}
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}
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__global__ void PReluScalarKernel(const float *input, const float *alpha,
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float *output, size_t spatial_size) {
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size_t offset = blockIdx.x * spatial_size;
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const float *in = input + offset;
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float scale = *alpha;
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float *out = output + offset;
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for (size_t i = threadIdx.x; i < spatial_size; i += blockDim.x) {
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float x = in[i];
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out[i] = (x > 0) ? x : scale * x;
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}
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}
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static inline void PReluChannelWise(cudaStream_t stream, const float *input,
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const float *alpha, float *output,
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int batch_size,
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const nvinfer1::Dims &dims) {
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size_t unroll = batch_size * dims.d[0];
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size_t spatial_size = dims.d[1] * dims.d[2];
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CHECK_LT(unroll, CUDA_MAX_NUM_BLOCKS);
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PReluChannelWiseKernel<<<unroll, CUDA_NUM_THREADS, 0, stream>>>(
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input, alpha, output, dims.d[0], spatial_size);
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}
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static inline void PReluElementWise(cudaStream_t stream, const float *input,
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const float *alpha, float *output,
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int batch_size,
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const nvinfer1::Dims &dims) {
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size_t unroll = batch_size * dims.d[0];
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size_t spatial_size = dims.d[1] * dims.d[2];
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CHECK_LT(unroll, CUDA_MAX_NUM_BLOCKS);
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PReluElementWiseKernel<<<unroll, CUDA_NUM_THREADS, 0, stream>>>(
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input, alpha, output, spatial_size);
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}
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static inline void PReluScalar(cudaStream_t stream, const float *input,
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const float *alpha, float *output,
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int batch_size, const nvinfer1::Dims &dims) {
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size_t unroll = batch_size * dims.d[0];
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size_t spatial_size = dims.d[1] * dims.d[2];
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CHECK_LT(unroll, CUDA_MAX_NUM_BLOCKS);
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PReluScalarKernel<<<unroll, CUDA_NUM_THREADS, 0, stream>>>(
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input, alpha, output, spatial_size);
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}
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nvinfer1::Dims PReluPlugin::getOutputDimensions(int index,
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const nvinfer1::Dims *inputDims,
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int nbInputs) {
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assert(nbInputs == 1);
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assert(index < this->getNbOutputs());
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nvinfer1::Dims const &input_dims = inputDims[0];
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nvinfer1::Dims output_dims = input_dims;
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return output_dims;
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}
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int PReluPlugin::enqueue(int batchSize, const void *const *inputs,
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void **outputs, void *workspace, cudaStream_t stream) {
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// input dims is CHW.
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const auto &input_dims = this->getInputDims(0);
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const float *input = reinterpret_cast<const float *>(inputs[0]);
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const float *alpha = reinterpret_cast<const float *>(alpha_.get().values);
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float *output = reinterpret_cast<float **>(outputs)[0];
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if (mode_ == "channel") {
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PReluChannelWise(stream, input, alpha, output, batchSize, input_dims);
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} else if (mode_ == "element") {
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PReluElementWise(stream, input, alpha, output, batchSize, input_dims);
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} else {
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PReluScalar(stream, input, alpha, output, batchSize, input_dims);
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}
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return cudaGetLastError() != cudaSuccess;
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}
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} // namespace tensorrt
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} // namespace inference
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} // namespace paddle
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// Copyright (c) 2018 PaddlePaddle Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <string>
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#include "paddle/fluid/inference/tensorrt/engine.h"
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#include "paddle/fluid/inference/tensorrt/plugin/trt_plugin.h"
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namespace paddle {
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namespace inference {
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namespace tensorrt {
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class PReluPlugin : public PluginTensorRT {
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TensorRTEngine::Weight alpha_;
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std::string mode_;
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protected:
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size_t getSerializationSize() override {
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// return getBaseSerializationSize(alpha_) + SerializedSize(mode_);
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return 0;
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}
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// TRT will call this func when we need to serialize the configuration of
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// tensorrt.
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// It should not be called by users.
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void serialize(void *buffer) override {
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// serializeBase(buffer);
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// SerializeValue(&buffer, alpha_);
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// SerializeValue(&buffer, mode_);
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}
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public:
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PReluPlugin(TensorRTEngine::Weight const &alpha, std::string const &mode)
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: alpha_(alpha), mode_(mode) {}
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// It was used for tensorrt deserialization.
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// It should not be called by users.
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PReluPlugin(void const *serialData, size_t serialLength) {
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// deserializeBase(serialData, serialLength);
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// DeserializeValue(&serialData, &serialLength, &alpha_);
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// DeserializeValue(&serialData, &serialLength, &mode_);
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}
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PReluPlugin *clone() const override { return new PReluPlugin(alpha_, mode_); }
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const char *getPluginType() const override { return "prelu"; }
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int getNbOutputs() const override { return 1; }
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nvinfer1::Dims getOutputDimensions(int index, const nvinfer1::Dims *inputs,
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int nbInputDims) override;
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int enqueue(int batchSize, const void *const *inputs, void **outputs,
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void *workspace, cudaStream_t stream) override;
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};
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} // namespace tensorrt
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} // namespace inference
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} // namespace paddle
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