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@ -16,6 +16,7 @@ limitations under the License. */
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#include <memory>
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#include <string>
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#include <vector>
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#include "paddle/fluid/framework/data_layout.h"
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#include "paddle/fluid/platform/cudnn_workspace_helper.h"
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#ifdef PADDLE_WITH_MKLDNN
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@ -25,12 +26,14 @@ limitations under the License. */
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namespace paddle {
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namespace operators {
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using DataLayout = framework::DataLayout;
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void ConvTransposeOp::InferShape(framework::InferShapeContext* ctx) const {
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PADDLE_ENFORCE(ctx->HasInput("Input"),
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PADDLE_ENFORCE_EQ(ctx->HasInput("Input"), true,
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"Input(Input) of ConvTransposeOp should not be null.");
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PADDLE_ENFORCE(ctx->HasInput("Filter"),
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PADDLE_ENFORCE_EQ(ctx->HasInput("Filter"), true,
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"Input(Filter) of ConvTransposeOp should not be null.");
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PADDLE_ENFORCE(ctx->HasOutput("Output"),
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PADDLE_ENFORCE_EQ(ctx->HasOutput("Output"), true,
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"Output(Output) of ConvTransposeOp should not be null.");
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auto in_dims = ctx->GetInputDim("Input");
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@ -41,52 +44,75 @@ void ConvTransposeOp::InferShape(framework::InferShapeContext* ctx) const {
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std::vector<int> paddings = ctx->Attrs().Get<std::vector<int>>("paddings");
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std::vector<int> dilations = ctx->Attrs().Get<std::vector<int>>("dilations");
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int groups = ctx->Attrs().Get<int>("groups");
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std::string padding_algorithm =
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ctx->Attrs().Get<std::string>("padding_algorithm");
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const DataLayout data_layout = framework::StringToDataLayout(
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ctx->Attrs().Get<std::string>("data_format"));
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PADDLE_ENFORCE(in_dims.size() == 4 || in_dims.size() == 5,
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PADDLE_ENFORCE_EQ(in_dims.size() == 4 || in_dims.size() == 5, true,
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"ConvTransposeOp intput should be 4-D or 5-D tensor.");
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PADDLE_ENFORCE_EQ(in_dims.size(), filter_dims.size(),
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"ConvTransposeOp input dimension and filter dimension "
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"should be the same.");
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PADDLE_ENFORCE(in_dims.size() - strides.size() == 2U,
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PADDLE_ENFORCE_EQ(
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in_dims.size() - strides.size(), 2U,
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"ConvTransposeOp input dimension and strides dimension should "
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"be consistent.");
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if (output_size.size())
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PADDLE_ENFORCE_EQ(output_size.size(), strides.size(),
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"ConvTransposeOp output_size dimension and strides "
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"dimension should be the same.");
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PADDLE_ENFORCE_EQ(paddings.size(), strides.size(),
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"ConvTransposeOp paddings dimension and strides "
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"dimension should be the same.");
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PADDLE_ENFORCE_EQ(paddings.size(), dilations.size(),
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"ConvTransposeOp paddings dimension and dilations "
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"dimension should be the same.");
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PADDLE_ENFORCE_EQ(in_dims[1], filter_dims[0],
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"In ConvTransposeOp, The number of input channels should "
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const int64_t C =
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(data_layout == DataLayout::kNCHW ? in_dims[1]
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: in_dims[in_dims.size() - 1]);
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PADDLE_ENFORCE_EQ(
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C, filter_dims[0],
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"The number of input channels of Op(ConvTransposeOp) should "
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"be equal to the number of filter's channels.");
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std::vector<int64_t> output_shape({in_dims[0], filter_dims[1] * groups});
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framework::DDim in_data_dims;
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if (data_layout == DataLayout::kNCHW) {
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in_data_dims = framework::slice_ddim(in_dims, 2, in_dims.size());
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} else {
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in_data_dims = framework::slice_ddim(in_dims, 1, in_dims.size() - 1);
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}
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framework::DDim filter_data_dims =
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framework::slice_ddim(filter_dims, 2, filter_dims.size());
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std::vector<int> ksize = framework::vectorize<int>(filter_data_dims);
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UpdatePaddingAndDilation(&paddings, &dilations, padding_algorithm,
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in_data_dims, strides, ksize);
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std::vector<int64_t> output_shape({in_dims[0]});
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if (data_layout == DataLayout::kNCHW) {
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output_shape.push_back(filter_dims[1] * groups);
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}
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const int offset = (data_layout == DataLayout::kNCHW ? 2 : 1);
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for (size_t i = 0; i < strides.size(); ++i) {
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auto filter_extent = dilations[i] * (filter_dims[i + 2] - 1) + 1;
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auto infer_shape =
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(in_dims[i + 2] - 1) * strides[i] - 2 * paddings[i] + filter_extent;
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auto infer_shape = (in_dims[i + offset] - 1) * strides[i] -
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paddings[2 * i] - paddings[2 * i + 1] + filter_extent;
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if (output_size.size()) {
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PADDLE_ENFORCE((output_size[i] >= infer_shape &&
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PADDLE_ENFORCE_EQ((output_size[i] >= infer_shape &&
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output_size[i] < infer_shape + strides[i]),
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"ConvTransposeOp output_size should be "
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true,
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"output_size of Op(ConvTransposeOp) should be "
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"in appropriate range.");
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output_shape.push_back(output_size[i]);
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} else {
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output_shape.push_back(infer_shape);
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}
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}
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if (data_layout == DataLayout::kNHWC) {
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output_shape.push_back(filter_dims[1] * groups);
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}
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ctx->SetOutputDim("Output", framework::make_ddim(output_shape));
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}
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framework::OpKernelType ConvTransposeOp::GetExpectedKernelType(
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const framework::ExecutionContext& ctx) const {
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framework::LibraryType library_{framework::LibraryType::kPlain};
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std::string data_format = ctx.Attr<std::string>("data_format");
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framework::DataLayout layout_ = framework::StringToDataLayout(data_format);
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framework::DataLayout layout_ = framework::DataLayout::kAnyLayout;
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bool use_cudnn = ctx.Attr<bool>("use_cudnn");
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use_cudnn &= platform::is_gpu_place(ctx.GetPlace());
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#ifdef PADDLE_WITH_CUDA
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@ -115,12 +141,11 @@ void Conv2DTransposeOpMaker::Make() {
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"(bool, default false) Set to true for inference only, false "
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"for training. Some layers may run faster when this is true.")
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.SetDefault(false);
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AddInput(
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"Input",
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AddInput("Input",
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"(Tensor) The input tensor of convolution transpose operator. "
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"The format of input tensor is NCHW. Where N is batch size, C is the "
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"number of input channels, H is the height of the feature, and "
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"W is the width of the feature.");
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"The format of input tensor is NCHW or NHWC. Where N is batch size, "
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"C is the number of input channels, H is the height of the feature, "
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"and W is the width of the feature.");
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AddInput(
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"Filter",
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"(Tensor) The filter tensor of convolution transpose operator. "
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@ -137,7 +162,7 @@ void Conv2DTransposeOpMaker::Make() {
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AddOutput("Output",
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"(Tensor) The output tensor of convolution transpose operator. "
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"The format of output tensor is also NCHW.");
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"The format of output tensor is the same as input tensor.");
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AddAttr<std::vector<int>>("output_size",
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"(vector<int> default: []), the "
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"size of the output tensor")
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@ -182,10 +207,15 @@ void Conv2DTransposeOpMaker::Make() {
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"data_format",
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"(string, default NCHW) Only used in "
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"An optional string from: \"NHWC\", \"NCHW\". "
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"Defaults to \"NHWC\". Specify the data format of the output data, "
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"the input will be transformed automatically. ")
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.SetDefault("AnyLayout");
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// TODO(dzhwinter): need to registered layout transform function
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"Specify that the data format of the input and output data is "
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"channel_first or channel_last.")
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.SetDefault("NCHW");
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AddAttr<std::string>(
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"padding_algorithm",
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"(string, default \"EXPLICIT\") An optional string from: \"EXPLICIT\","
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"\"SAME\",\"VALID\". Set to \"EXPLICIT\" for explicit padding. "
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"Set to \"SAME\" or \"VALID\" for algorithm of padding. ")
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.SetDefault("EXPLICIT");
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AddAttr<int>("workspace_size_MB",
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"Used in cudnn kernel only. workspace size for cudnn, in MB, "
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"workspace is a section of GPU memory which will be "
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@ -199,7 +229,7 @@ Convolution2D Transpose Operator.
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The convolution transpose operation calculates the output based on the input, filter
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and dilations, strides, paddings, groups parameters. The size of each dimension of the
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parameters is checked in the infer-shape.
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Input(Input) and output(Output) are in NCHW format. Where N is batchsize, C is the
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Input(Input) and output(Output) are in NCHW or NHWC format. Where N is batchsize, C is the
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number of channels, H is the height of the feature, and W is the width of the feature.
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Filter(Input) is in MCHW format. Where M is the number of input feature channels,
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C is the number of output feature channels, H is the height of the filter,
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@ -216,19 +246,19 @@ For an example:
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Output shape: $(N, C_{out}, H_{out}, W_{out})$
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Where
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$$
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H_{out} = (H_{in} - 1) * strides[0] - 2 * paddings[0] + dilations[0] * (H_f - 1) + 1 \\
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W_{out} = (W_{in} - 1) * strides[1] - 2 * paddings[1] + dilations[1] * (W_f - 1) + 1
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H_{out} = (H_{in} - 1) * strides[0] - pad_height_top - pad_height_bottom + dilations[0] * (H_f - 1) + 1 \\
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W_{out} = (W_{in} - 1) * strides[1] - pad_width_left - pad_width_right + dilations[1] * (W_f - 1) + 1
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$$
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)DOC");
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}
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void Conv3DTransposeOpMaker::Make() {
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AddInput("Input",
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AddInput(
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"Input",
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"(Tensor) The input tensor of convolution transpose operator."
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"The format of input tensor is NCDHW. Where N is batch size, C is "
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"the number of channels, D is the depth of the feature, H is the "
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"height of the feature, and "
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"W is the width of the feature.");
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"The format of input tensor is NCDHW or NDHWC. Where N is batch "
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"size, C is the number of channels, D is the depth of the feature, "
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"H is the height of the feature, and W is the width of the feature.");
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AddInput("Filter",
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"(Tensor) The filter tensor of convolution transpose operator."
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"The format of the filter tensor is MCDHW, where M is the number of "
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@ -240,7 +270,7 @@ void Conv3DTransposeOpMaker::Make() {
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"the convolution3d transpose scenario.");
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AddOutput("Output",
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"(Tensor) The output tensor of convolution transpose operator."
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"The format of output tensor is also NCDHW."
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"The format of output tensor is the same as input tensor."
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"Where N is batch size, C is "
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"the number of channels, D is the depth of the feature, H is the "
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"height of the feature, and W is the width of the feature.");
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@ -278,10 +308,15 @@ void Conv3DTransposeOpMaker::Make() {
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"data_format",
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"(string, default NCHW) Only used in "
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"An optional string from: \"NHWC\", \"NCHW\". "
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"Defaults to \"NHWC\". Specify the data format of the output data, "
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"the input will be transformed automatically. ")
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.SetDefault("AnyLayout");
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// TODO(dzhwinter): need to registered layout transform function
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"Specify that the data format of the input and output data is "
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"channel_first or channel_last.")
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.SetDefault("NCHW");
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AddAttr<std::string>(
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"padding_algorithm",
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"(string, default \"EXPLICIT\") An optional string from: \"EXPLICIT\","
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"\"SAME\",\"VALID\". Set to \"EXPLICIT\" for explicit padding. "
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"Set to \"SAME\" or \"VALID\" for algorithm of padding. ")
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.SetDefault("EXPLICIT");
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AddAttr<int>("workspace_size_MB",
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"Used in cudnn kernel only. workspace size for cudnn, in MB, "
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"workspace is a section of GPU memory which will be "
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@ -295,7 +330,7 @@ Convolution3D Transpose Operator.
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The convolution transpose operation calculates the output based on the input, filter
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and dilations, strides, paddings, groups parameters. The size of each dimension of the
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parameters is checked in the infer-shape.
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Input(Input) and output(Output) are in NCDHW format. Where N is batch size, C is the
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Input(Input) and output(Output) are in NCDHW or NDHWC format. Where N is batch size, C is the
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number of channels, D is the depth of the feature, H is the height of the feature,
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and W is the width of the feature.
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Filter(Input) is in MCDHW format. Where M is the number of input feature channels,
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@ -313,9 +348,9 @@ Example:
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Output shape: $(N, C_{out}, D_{out}, H_{out}, W_{out})$
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Where
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$$
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D_{out} = (D_{in} - 1) * strides[0] - 2 * paddings[0] + dilations[0] * (D_f - 1) + 1 \\
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H_{out} = (H_{in} - 1) * strides[1] - 2 * paddings[1] + dilations[1] * (H_f - 1) + 1 \\
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W_{out} = (W_{in} - 1) * strides[2] - 2 * paddings[2] + dilations[2] * (W_f - 1) + 1
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D_{out} = (D_{in} - 1) * strides[0] - pad_depth_front - pad_depth_back + dilations[0] * (D_f - 1) + 1 \\
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H_{out} = (H_{in} - 1) * strides[1] - pad_height_top - pad_height_bottom + dilations[1] * (H_f - 1) + 1 \\
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W_{out} = (W_{in} - 1) * strides[2] - pad_width_left - pad_width_right + dilations[2] * (W_f - 1) + 1
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$$
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)DOC");
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}
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@ -348,8 +383,7 @@ framework::OpKernelType ConvTransposeOpGrad::GetExpectedKernelType(
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library_ = framework::LibraryType::kPlain;
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}
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std::string data_format = ctx.Attr<std::string>("data_format");
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framework::DataLayout layout_ = framework::StringToDataLayout(data_format);
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framework::DataLayout layout_ = framework::DataLayout::kAnyLayout;
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return framework::OpKernelType(ctx.Input<Tensor>("Input")->type(),
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ctx.GetPlace(), layout_, library_);
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}
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Zhang Ting
6 years ago
committed by
hong