[MSLITE] mnet full quant bug

4 years ago · 3fd7bc78c2
parent bedc733e42
commit 3fd7bc78c2
2 changed files with 4 additions and 4 deletions
--- a/mindspore/lite/nnacl/assembly/arm64/PreSum4x16Int8Peroc.S
+++ b/mindspore/lite/nnacl/assembly/arm64/PreSum4x16Int8Peroc.S
@ -104,11 +104,11 @@ OcRes4_1:
  b OcRes4End
 OcRes4_2:
-  ld1 {v15.h}[0], [x16]
+  ld1 {v15.d}[0], [x16]
  b OcRes4End
 OcRes4_3:
-  ld1 {v15.h}[0], [x16]
+  ld1 {v15.d}[0], [x16]
  add x16, x16, #8
  ld1 {v15.s}[2], [x16]
  b OcRes4End
--- a/mindspore/lite/nnacl/int8/conv_int8.c
+++ b/mindspore/lite/nnacl/int8/conv_int8.c
@ -406,12 +406,12 @@ void Conv1x1PreOptPeroc(const int8_t *src_input, int8_t *packed_input, int32_t *
      "14: \n"
      "ld1 {v16.4s}, [x10], #16\n"
-      "ld1 {v17.h}[0], [x10] \n"
+      "ld1 {v17.d}[0], [x10] \n"
      "b 16f \n"
      "15: \n"
      "ld1 {v16.4s}, [x10], #16\n"
-      "ld1 {v17.h}[0], [x10] \n"
+      "ld1 {v17.d}[0], [x10] \n"
      "add x10, x10, #8 \n"
      "ld1 {v17.s}[2], [x10] \n"
      "b 16f \n"