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cpu_pad_op

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pull/12189/head
wanyiming 4 years ago
parent 66e5e1cfc3
commit dbc0ad13db
9 changed files with 1270 additions and 0 deletions
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192
mindspore/ccsrc/backend/kernel_compiler/cpu/mirror_pad_cpu_kernel.cc
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/**
* Copyright 2021 Huawei Technologies Co., Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "backend/kernel_compiler/cpu/mirror_pad_cpu_kernel.h"
#include "runtime/device/cpu/cpu_device_address.h"
namespace mindspore {
namespace kernel {
void MirrorPadCPUKernel::InitKernel(const CNodePtr &kernel_node) {
std::string mode = AnfAlgo::GetNodeAttr<std::string>(kernel_node, "mode");
dtype_ = AnfAlgo::GetPrevNodeOutputInferDataType(kernel_node, 0);
if (mode == "REFLECT") {
mode_ = 0;
} else if (mode == "SYMMETRIC") {
mode_ = 1;
} else {
MS_LOG(EXCEPTION) << "For mirror pad, only REFLECT and SYMMETRIC are supported.";
}
std::vector<size_t> input_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
shape_size_ = input_shape.size();
if (shape_size_ == 4) { // shape adjustment from 2d/3d to 4d
} else if (shape_size_ == 3) {
auto it = input_shape.begin();
input_shape.insert(it, 1); // batch padding
shape_size_ = 4;
} else if (shape_size_ == 2) {
auto it = input_shape.begin();
input_shape.insert(it, 2, 1); // channel padding
shape_size_ = 4;
}
for (size_t i = 0; i < shape_size_; ++i) {
tensor_size_ *= input_shape[i];
input_shape_.push_back(input_shape[i]);
}
std::vector<size_t> padding_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 1);
num_paddings_ = padding_shape[0];
auto output_shape = AnfAlgo::GetOutputInferShape(kernel_node, 0);
for (auto x : output_shape) {
output_size_ *= x;
output_shape_.push_back(x);
}
size_t max_width = input_shape_[3];
size_t max_height = input_shape_[2];
if (mode_ == 1) { // symmetric
max_width = max_width + (2 * max_width);
max_height = max_height + (2 * max_height);
} else { // reflect
max_width = max_width + (2 * (max_width - 1));
max_height = max_height + (2 * (max_height - 1));
}
if (output_shape_[(output_shape_.size() - 2) + 0] > max_height ||
output_shape_[(output_shape_.size() - 2) + 1] > max_width) {
MS_LOG(ERROR) << "ERROR: Padding value too high for input Tensor on 1 or more dims";
}
}
void extract_paddings(const int64_t *paddings_arg, int padd_dim, int64_t *extracted_paddings) {
const int paddings_offset = MAX_PADDINGS - padd_dim;
for (int i = 0; i < padd_dim; i++) {
extracted_paddings[(paddings_offset + i) * PADDING_SIZE] = paddings_arg[i * PADDING_SIZE];
extracted_paddings[(paddings_offset + i) * PADDING_SIZE + 1] = paddings_arg[i * PADDING_SIZE + 1];
}
}
bool MirrorPadCPUKernel::Launch(const std::vector<kernel::AddressPtr> &inputs,
const std::vector<kernel::AddressPtr> & /*workspace*/,
const std::vector<kernel::AddressPtr> &outputs) {
if (dtype_ == kNumberTypeFloat16) {
LaunchKernel<float16>(inputs, outputs);
} else if (dtype_ == kNumberTypeFloat32) {
LaunchKernel<float>(inputs, outputs);
} else if (dtype_ == kNumberTypeInt32) {
LaunchKernel<int>(inputs, outputs);
} else {
MS_LOG(EXCEPTION) << "Data type is " << TypeIdLabel(dtype_) << "is not support.";
}
return true;
}
template <typename T>
void MirrorPadCPUKernel::LaunchKernel(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &outputs) {
auto inputs_addr = reinterpret_cast<T *>(inputs[0]->addr);
int64_t *paddings_arg = reinterpret_cast<int64_t *>(inputs[1]->addr);
auto outputs_addr = reinterpret_cast<T *>(outputs[0]->addr);
const int old_batch = input_shape_[0];
const int old_channel = input_shape_[1];
const int old_height = input_shape_[2];
const int old_width = input_shape_[3];
int dim_offset = output_shape_.size() - 2;
const int padded_height = output_shape_[dim_offset + 0];
const int padded_width = output_shape_[dim_offset + 1];
const int padd_dim = num_paddings_;
const int mode = mode_;
int64_t paddings[MAX_PADDINGS * PADDING_SIZE]; // local and fixed size to keep in registers
for (int i = 0; i < MAX_PADDINGS * PADDING_SIZE; i++) {
paddings[i] = 0;
}
extract_paddings(paddings_arg, padd_dim, paddings);
// Create anchor points for non mirrored data inside new tensor
int ap1_x = paddings[WIDTH + LEFT];
int ap2_x = paddings[WIDTH + LEFT] + old_width - 1;
int ap1_y = paddings[HEIGHT + TOP];
int ap2_y = paddings[HEIGHT + TOP] + old_height - 1;
int ap1_channel = paddings[CHANNEL + LEFT];
int ap2_channel = paddings[CHANNEL + LEFT] + old_channel - 1;
int ap1_batch = paddings[BATCH + LEFT];
int ap2_batch = paddings[BATCH + LEFT] + old_batch - 1;
int channels_new = old_channel + paddings[CHANNEL + LEFT] + paddings[CHANNEL + RIGHT];
for (size_t pos = 0; pos < output_size_; ++pos) {
int block_num = (pos / padded_width) / padded_height;
// cur position
const int padded_x = pos % padded_width;
const int padded_y = (pos / padded_width) % padded_height;
const int padded_channel = block_num % channels_new;
const int padded_batch = block_num / channels_new;
// data to mirror from in new tensor dims
int matchval_x_index = padded_x;
int matchval_y_index = padded_y;
int matchval_channel_index = padded_channel;
int matchval_batch_index = padded_batch;
int equiv_block_num = 0;
// update matching index in original tensor across all 4 dims
if ((padded_x < ap1_x) || (padded_x > ap2_x)) {
int x_dist = (padded_x < ap1_x) ? (ap1_x - padded_x) : (padded_x - ap2_x);
matchval_x_index = (padded_x < ap1_x) ? (ap1_x + x_dist - mode) : (ap2_x - x_dist + mode);
}
if ((padded_y < ap1_y) || (padded_y > ap2_y)) {
int y_dist = (padded_y < ap1_y) ? (ap1_y - padded_y) : (padded_y - ap2_y);
matchval_y_index = (padded_y < ap1_y) ? (ap1_y + y_dist - mode) : (ap2_y - y_dist + mode);
}
if ((padded_channel < ap1_channel) || (padded_channel > ap2_channel)) {
int channel_dist =
(padded_channel < ap1_channel) ? (ap1_channel - padded_channel) : (padded_channel - ap2_channel);
matchval_channel_index =
(padded_channel < ap1_channel) ? (ap1_channel + channel_dist - mode) : (ap2_channel - channel_dist + mode);
}
if ((padded_batch < ap1_batch) || (padded_batch > ap2_batch)) {
int batch_dist = (padded_batch < ap1_batch) ? (ap1_batch - padded_batch) : (padded_batch - ap2_batch);
matchval_batch_index =
(padded_batch < ap1_batch) ? (ap1_batch + batch_dist - mode) : (ap2_batch - batch_dist + mode);
}
// calculate equivalent block in input
equiv_block_num = ((matchval_batch_index - paddings[BATCH + LEFT]) * old_channel) +
(matchval_channel_index - paddings[CHANNEL + LEFT]);
// copy data from equiv block and adjusted x and y values in unpadded tensor
outputs_addr[pos] =
inputs_addr[(equiv_block_num * old_height + matchval_y_index - paddings[HEIGHT + TOP]) * old_width +
matchval_x_index - paddings[WIDTH + LEFT]];
}
}
void MirrorPadCPUKernel::CheckParam(const CNodePtr &kernel_node) {
size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
if (input_num != 2) {
MS_LOG(EXCEPTION) << "Input number is " << input_num << ", but MirrorPadCPUKernel needs 2 inputs.";
}
size_t output_num = AnfAlgo::GetOutputTensorNum(kernel_node);
if (output_num != 1) {
MS_LOG(EXCEPTION) << "Output number is " << output_num << ", but MirrorPadCPUKernel needs 1 output.";
}
}
} // namespace kernel
} // namespace mindspore

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mindspore/ccsrc/backend/kernel_compiler/cpu/mirror_pad_cpu_kernel.h
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/**
* Copyright 2021 Huawei Technologies Co., Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_MIRROR_PAD_CPU_KERNEL_H_
#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_MIRROR_PAD_CPU_KERNEL_H_
#include <memory>
#include <unordered_map>
#include <vector>
#include <string>
#include "backend/kernel_compiler/cpu/cpu_kernel.h"
#include "backend/kernel_compiler/cpu/cpu_kernel_factory.h"
// preset size of paddings
#define MAX_PADDINGS 4
#define PADDING_SIZE 2
// define constants for kernel indexing use
#define BATCH 0 * PADDING_SIZE
#define CHANNEL 1 * PADDING_SIZE
#define HEIGHT 2 * PADDING_SIZE
#define WIDTH 3 * PADDING_SIZE
#define TOP 0
#define BOTTOM 1
#define LEFT 0
#define RIGHT 1
namespace mindspore {
namespace kernel {
class MirrorPadCPUKernel : public CPUKernel {
public:
MirrorPadCPUKernel() = default;
~MirrorPadCPUKernel() override = default;
void InitKernel(const CNodePtr &kernel_node) override;
bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
const std::vector<AddressPtr> &outputs) override;
template <typename T>
void LaunchKernel(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &outputs);
private:
void CheckParam(const CNodePtr &kernel_node);
TypeId dtype_{kTypeUnknown};
uint64_t tensor_size_ = 1;
size_t shape_size_;
uint64_t output_size_ = 1;
std::vector<size_t> input_shape_;
std::vector<size_t> output_shape_;
int mode_;
int num_paddings_;
};
MS_REG_CPU_KERNEL(
MirrorPad,
KernelAttr().AddInputAttr(kNumberTypeFloat16).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat16),
MirrorPadCPUKernel);
MS_REG_CPU_KERNEL(
MirrorPad,
KernelAttr().AddInputAttr(kNumberTypeFloat32).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat32),
MirrorPadCPUKernel);
MS_REG_CPU_KERNEL(
MirrorPad, KernelAttr().AddInputAttr(kNumberTypeInt32).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeInt32),
MirrorPadCPUKernel);
} // namespace kernel
} // namespace mindspore
#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_MIRROR_PAD_CPU_KERNEL_H_

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mindspore/ccsrc/backend/kernel_compiler/cpu/mirror_pad_grad_cpu_kernel.cc
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mindspore/ccsrc/backend/kernel_compiler/cpu/mirror_pad_grad_cpu_kernel.h
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/**
* Copyright 2021 Huawei Technologies Co., Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_MIRROR_PAD_GRAD_CPU_KERNEL_H_
#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_MIRROR_PAD_GRAD_CPU_KERNEL_H_
#include <memory>
#include <unordered_map>
#include <vector>
#include <string>
#include "backend/kernel_compiler/cpu/cpu_kernel.h"
#include "backend/kernel_compiler/cpu/cpu_kernel_factory.h"
// preset size of paddings
#define MAX_PADDINGS 4
#define PADDING_SIZE 2
// define constants for kernel indexing use
#define BATCH 0 * PADDING_SIZE
#define CHANNEL 1 * PADDING_SIZE
#define HEIGHT 2 * PADDING_SIZE
#define WIDTH 3 * PADDING_SIZE
#define TOP 0
#define BOTTOM 1
#define LEFT 0
#define RIGHT 1
namespace mindspore {
namespace kernel {
class MirrorPadGradCPUKernel : public CPUKernel {
public:
MirrorPadGradCPUKernel() = default;
~MirrorPadGradCPUKernel() override = default;
void InitKernel(const CNodePtr &kernel_node) override;
void InitInputOutputSize(const CNodePtr &kernel_node) override;
bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
const std::vector<AddressPtr> &outputs) override;
template <typename T>
void InitWorkspaceSize();
template <typename T>
void LaunchKernel(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
const std::vector<AddressPtr> &outputs);
template <typename T>
void MirrorPadGrad_Width_Height(const size_t size, const T *dy, T *interim_dy, const int dx_batches,
const int dx_channels, const int dx_height, const int dx_width, const int dy_height,
const int dy_width, const int padd_dim, const int64_t *paddings_arg, int mode, T *dx);
template <typename T>
void MirrorPadGradBatchChannel(const size_t size, T *dy, T *interim_dy, const int dx_batches, const int dx_channels,
const int dx_height, const int dx_width, const int dy_height, const int dy_width,
const int padd_dim, const int64_t *paddings_arg, int mode, T *dx);
private:
void CheckParam(const CNodePtr &kernel_node);
TypeId dtype_{kTypeUnknown};
size_t tensor_size_ = 1;
size_t shape_size_;
size_t output_size_ = 1;
size_t workspace_size_ = 1;
std::vector<size_t> input_shape_;
std::vector<size_t> output_shape_;
int mode_;
int num_paddings_;
};
MS_REG_CPU_KERNEL(
MirrorPadGrad,
KernelAttr().AddInputAttr(kNumberTypeFloat16).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat16),
MirrorPadGradCPUKernel);
MS_REG_CPU_KERNEL(
MirrorPadGrad,
KernelAttr().AddInputAttr(kNumberTypeFloat32).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeFloat32),
MirrorPadGradCPUKernel);
MS_REG_CPU_KERNEL(
MirrorPadGrad,
KernelAttr().AddInputAttr(kNumberTypeInt32).AddInputAttr(kNumberTypeInt64).AddOutputAttr(kNumberTypeInt32),
MirrorPadGradCPUKernel);
} // namespace kernel
} // namespace mindspore
#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_MIRROR_PAD_CPU_KERNEL_H_

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mindspore/ccsrc/backend/kernel_compiler/cpu/pad_cpu_kernel.cc
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/**
* Copyright 2021 Huawei Technologies Co., Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "backend/kernel_compiler/cpu/pad_cpu_kernel.h"
#include "runtime/device/cpu/cpu_device_address.h"
namespace mindspore {
namespace kernel {
void PadCPUKernel::InitKernel(const CNodePtr &kernel_node) {
paddings_ = AnfAlgo::GetNodeAttr<std::vector<std::vector<int64_t>>>(kernel_node, "paddings");
dtype_ = AnfAlgo::GetPrevNodeOutputInferDataType(kernel_node, 0);
std::vector<size_t> input_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
shape_size_ = input_shape.size();
if (shape_size_ == 4) { // shape adjustment from 2d/3d to 4d
} else if (shape_size_ == 3) {
auto it = input_shape.begin();
input_shape.insert(it, 1); // batch padding
shape_size_ = 4;
} else if (shape_size_ == 2) {
auto it = input_shape.begin();
input_shape.insert(it, 2, 1); // channel padding
shape_size_ = 4;
}
for (size_t i = 0; i < shape_size_; ++i) {
tensor_size_ *= input_shape[i];
input_shape_.push_back(input_shape[i]);
}
if (paddings_.size() == 4) { // shape adjustment from 2d/3d to 4d
} else if (paddings_.size() == 3) {
auto it = paddings_.begin();
paddings_.insert(it, 1, {0, 0}); // batch padding
} else if (paddings_.size() == 2) {
auto it = paddings_.begin();
paddings_.insert(it, 2, {0, 0}); // channel padding
}
for (size_t i = 0; i < shape_size_; i++) {
size_t temp = input_shape[i] + (paddings_[i][0] + paddings_[i][1]); // compute new dim size
output_size_ *= temp;
output_shape_.push_back(temp); // correct new dimension size
}
}
bool PadCPUKernel::Launch(const std::vector<kernel::AddressPtr> &inputs,
const std::vector<kernel::AddressPtr> & /*workspace*/,
const std::vector<kernel::AddressPtr> &outputs) {
if (dtype_ == kNumberTypeFloat16) {
LaunchKernel<float16>(inputs, outputs);
} else if (dtype_ == kNumberTypeFloat32) {
LaunchKernel<float>(inputs, outputs);
} else if (dtype_ == kNumberTypeInt32) {
LaunchKernel<int>(inputs, outputs);
} else {
MS_LOG(EXCEPTION) << "Data type is " << TypeIdLabel(dtype_) << "is not support.";
}
return true;
}
template <typename T>
void PadCPUKernel::LaunchKernel(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &outputs) {
auto inputs_addr = reinterpret_cast<T *>(inputs[0]->addr);
auto outputs_addr = reinterpret_cast<T *>(outputs[0]->addr);
const int pad_left = paddings_[3][0];
const int pad_top = paddings_[2][0];
const int pad_channel_before = paddings_[1][0];
const int pad_channel_after = paddings_[1][1];
const T pad_value = T(0);
// const int num = input_shape_[0];
const int channels_orig = input_shape_[1];
const int old_height = input_shape_[2];
const int old_width = input_shape_[3];
const int padded_height = output_shape_[2];
const int padded_width = output_shape_[3];
for (size_t pos = 0; pos < output_size_; ++pos) {
int block_num = (pos / padded_width) / padded_height;
const int padded_w = pos % padded_width; // x coordinate referred to by cur 'pos'
const int padded_h = (pos / padded_width) % padded_height; // y coordinate referred to by cur 'pos'
int channels_new = channels_orig + pad_channel_after + pad_channel_before; // new number of channels from padding
int channel_num = block_num % channels_new; // current channel
int batch_item = block_num / channels_new; // current item in batch
if (padded_h - pad_top < 0 || padded_w - pad_left < 0 || padded_h - pad_top >= old_height ||
padded_w - pad_left >= old_width || channel_num <= pad_channel_before - 1 ||
channel_num > channels_orig + pad_channel_before - 1) {
outputs_addr[pos] = pad_value;
} else {
// on a block/x,y position that isn't padding, copy data from the correct block/x,y pos the input
// calculate from number of blocks of padding (due to channel padding) inserted prior
int equiv_block_num = block_num - (batch_item * (pad_channel_before + pad_channel_after)) - pad_channel_before;
outputs_addr[pos] =
inputs_addr[(equiv_block_num * old_height + padded_h - pad_top) * old_width + padded_w - pad_left];
}
}
}
void PadCPUKernel::CheckParam(const CNodePtr &kernel_node) {
size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
if (input_num != 1) {
MS_LOG(EXCEPTION) << "Input number is " << input_num << ", but PadCPUKernel needs 1 input.";
}
size_t output_num = AnfAlgo::GetOutputTensorNum(kernel_node);
if (output_num != 1) {
MS_LOG(EXCEPTION) << "Output number is " << output_num << ", but PadCPUKernel needs 1 output.";
}
}
} // namespace kernel
} // namespace mindspore

58
mindspore/ccsrc/backend/kernel_compiler/cpu/pad_cpu_kernel.h
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/**
* Copyright 2021 Huawei Technologies Co., Ltd
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_PAD_CPU_KERNEL_H_
#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_PAD_CPU_KERNEL_H_
#include <memory>
#include <unordered_map>
#include <vector>
#include "backend/kernel_compiler/cpu/cpu_kernel.h"
#include "backend/kernel_compiler/cpu/cpu_kernel_factory.h"
namespace mindspore {
namespace kernel {
class PadCPUKernel : public CPUKernel {
public:
PadCPUKernel() = default;
~PadCPUKernel() override = default;
void InitKernel(const CNodePtr &kernel_node) override;
bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
const std::vector<AddressPtr> &outputs) override;
template <typename T>
void LaunchKernel(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &outputs);
private:
void CheckParam(const CNodePtr &kernel_node);
std::vector<std::vector<int64_t>> paddings_;
TypeId dtype_{kTypeUnknown};
uint64_t tensor_size_ = 1;
size_t shape_size_ = 1;
uint64_t output_size_ = 1;
std::vector<size_t> input_shape_;
std::vector<size_t> output_shape_;
};
MS_REG_CPU_KERNEL(Pad, KernelAttr().AddInputAttr(kNumberTypeFloat16).AddOutputAttr(kNumberTypeFloat16), PadCPUKernel);
MS_REG_CPU_KERNEL(Pad, KernelAttr().AddInputAttr(kNumberTypeFloat32).AddOutputAttr(kNumberTypeFloat32), PadCPUKernel);
MS_REG_CPU_KERNEL(Pad, KernelAttr().AddInputAttr(kNumberTypeInt32).AddOutputAttr(kNumberTypeInt32), PadCPUKernel);
} // namespace kernel
} // namespace mindspore
#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_CPU_PAD_CPU_KERNEL_H_

3
mindspore/ccsrc/backend/kernel_compiler/cpu/slice_cpu_kernel.h
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@ -53,8 +53,11 @@ class SliceCPUKernel : public CPUKernel {
MS_REG_CPU_KERNEL(Slice, KernelAttr().AddInputAttr(kNumberTypeFloat32).AddOutputAttr(kNumberTypeFloat32),
SliceCPUKernel);
MS_REG_CPU_KERNEL(Slice, KernelAttr().AddInputAttr(kNumberTypeInt32).AddOutputAttr(kNumberTypeInt32), SliceCPUKernel);
MS_REG_CPU_KERNEL(StridedSlice, KernelAttr().AddInputAttr(kNumberTypeFloat32).AddOutputAttr(kNumberTypeFloat32),
SliceCPUKernel);
MS_REG_CPU_KERNEL(StridedSlice, KernelAttr().AddInputAttr(kNumberTypeInt32).AddOutputAttr(kNumberTypeInt32),
SliceCPUKernel);
} // namespace kernel
} // namespace mindspore

169
tests/st/ops/cpu/test_mirror_pad.py
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# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ============================================================================
import pytest
import numpy as np
import mindspore
import mindspore.nn as nn
import mindspore.context as context
from mindspore import Tensor
from mindspore.ops.composite import GradOperation
@pytest.mark.level0
@pytest.mark.platform_x86_cpu_training
@pytest.mark.env_onecard
def test_mirror_pad():
context.set_context(mode=context.GRAPH_MODE, device_target="CPU")
test1_arr_in = [[[[1, 2, 3], [4, 5, 6], [7, 8, 9]]]]
test_1_paddings = ((0, 0), (0, 0), (1, 1), (2, 2))
test1_arr_exp = [[[[6, 5, 4, 5, 6, 5, 4], [3, 2, 1, 2, 3, 2, 1], [6, 5, 4, 5, 6, 5, 4],
[9, 8, 7, 8, 9, 8, 7], [6, 5, 4, 5, 6, 5, 4]]]]
test2_arr_in = [[[[1, 2, 3], [4, 5, 6], [7, 8, 9]]]]
test_2_paddings = ((0, 0), (0, 0), (1, 1), (2, 2))
test2_arr_exp = [[[[2, 1, 1, 2, 3, 3, 2], [2, 1, 1, 2, 3, 3, 2], [5, 4, 4, 5, 6, 6, 5],
[8, 7, 7, 8, 9, 9, 8], [8, 7, 7, 8, 9, 9, 8]]]]
reflectOp = nn.Pad(mode='REFLECT', paddings=test_1_paddings)
symmOp = nn.Pad(mode='SYMMETRIC', paddings=test_2_paddings)
x_test_1 = Tensor(np.array(test1_arr_in), dtype=mindspore.float32)
x_test_2 = Tensor(np.array(test2_arr_in), dtype=mindspore.float32)
y_test_1 = reflectOp(x_test_1).asnumpy()
y_test_2 = symmOp(x_test_2).asnumpy()
print(np.array(test1_arr_in))
print(y_test_1)
np.testing.assert_equal(np.array(test1_arr_exp), y_test_1)
np.testing.assert_equal(np.array(test2_arr_exp), y_test_2)
class Grad(nn.Cell):
def __init__(self, network):
super(Grad, self).__init__()
self.grad = GradOperation(get_all=True, sens_param=True)
self.network = network
def construct(self, input_, output_grad):
return self.grad(self.network)(input_, output_grad)
class Net(nn.Cell):
def __init__(self, pads, mode_):
super(Net, self).__init__()
self.pad = nn.Pad(mode=mode_, paddings=pads)
def construct(self, x):
return self.pad(x)
@pytest.mark.level0
@pytest.mark.platform_x86_cpu_training
@pytest.mark.env_onecard
def test_mirror_pad_backprop():
context.set_context(mode=context.GRAPH_MODE, device_target="CPU")
test_arr_in = [[[[1, 2, 3], [4, 5, 6], [7, 8, 9]]]] # size -> 3*3
test_arr_in = Tensor(test_arr_in, dtype=mindspore.float32)
dy = (np.ones((1, 1, 4, 5)) * 0.1).astype(np.float32)
expected_dx = np.array([[[[0.2, 0.2, 0.1],
[0.4, 0.4, 0.2],
[0.2, 0.2, 0.1]]]])
net = Grad(Net(((0, 0), (0, 0), (1, 0), (0, 2)), "REFLECT"))
dx = net(test_arr_in, Tensor(dy))
dx = dx[0].asnumpy()
np.testing.assert_array_almost_equal(dx, expected_dx)
@pytest.mark.level0
@pytest.mark.platform_x86_gpu_training
@pytest.mark.env_onecard
def test_mirror_pad_fwd_back_4d_int32_reflect():
context.set_context(mode=context.GRAPH_MODE, device_target="CPU")
# set constants
shape = (2, 3, 3, 5)
pads = ((1, 0), (2, 0), (1, 2), (3, 4))
total_val = np.prod(shape)
test_arr_np = np.arange(total_val).reshape(shape) + 1
test_arr_ms = Tensor(test_arr_np, dtype=mindspore.int32)
# fwd_pass_check
op = nn.Pad(mode="REFLECT", paddings=pads)
expected_np_result = np.pad(test_arr_np, pads, 'reflect')
obtained_ms_res = op(test_arr_ms).asnumpy()
np.testing.assert_array_equal(expected_np_result, obtained_ms_res)
# backwards pass check
GradNet = Grad(Net(pads, "REFLECT"))
dy_value = Tensor(np.ones(obtained_ms_res.shape), dtype=mindspore.int32)
dx_value_obtained = GradNet(test_arr_ms, dy_value)[0].asnumpy()
dx_value_expected = np.array([[[[4, 6, 6, 6, 2],
[6, 9, 9, 9, 3],
[2, 3, 3, 3, 1]],
[[8, 12, 12, 12, 4],
[12, 18, 18, 18, 6],
[4, 6, 6, 6, 2]],
[[8, 12, 12, 12, 4],
[12, 18, 18, 18, 6],
[4, 6, 6, 6, 2]]],
[[[8, 12, 12, 12, 4],
[12, 18, 18, 18, 6],
[4, 6, 6, 6, 2]],
[[16, 24, 24, 24, 8],
[24, 36, 36, 36, 12],
[8, 12, 12, 12, 4]],
[[16, 24, 24, 24, 8],
[24, 36, 36, 36, 12],
[8, 12, 12, 12, 4]]]], dtype=np.int32)
np.testing.assert_array_equal(dx_value_expected, dx_value_obtained)
@pytest.mark.level0
@pytest.mark.platform_x86_cpu_training
@pytest.mark.env_onecard
def test_mirror_pad_fwd_back_4d_int32_symm():
context.set_context(mode=context.GRAPH_MODE, device_target="CPU")
# set constants
shape = (2, 3, 3, 5)
pads = ((1, 0), (2, 0), (1, 2), (3, 4))
total_val = np.prod(shape)
test_arr_np = np.arange(total_val).reshape(shape) + 1
test_arr_ms = Tensor(test_arr_np, dtype=mindspore.int32)
# fwd_pass_check
op = nn.Pad(mode="SYMMETRIC", paddings=pads)
expected_np_result = np.pad(test_arr_np, pads, 'symmetric')
obtained_ms_res = op(test_arr_ms).asnumpy()
np.testing.assert_array_equal(expected_np_result, obtained_ms_res)
# backwards pass check
GradNet = Grad(Net(pads, "SYMMETRIC"))
dy_value = Tensor(np.ones(obtained_ms_res.shape), dtype=mindspore.int32)
dx_value_obtained = GradNet(test_arr_ms, dy_value)[0].asnumpy()
dx_value_expected = np.array([[[[16, 24, 24, 16, 16],
[16, 24, 24, 16, 16],
[16, 24, 24, 16, 16]],
[[16, 24, 24, 16, 16],
[16, 24, 24, 16, 16],
[16, 24, 24, 16, 16]],
[[8, 12, 12, 8, 8],
[8, 12, 12, 8, 8],
[8, 12, 12, 8, 8]]],
[[[8, 12, 12, 8, 8],
[8, 12, 12, 8, 8],
[8, 12, 12, 8, 8]],
[[8, 12, 12, 8, 8],
[8, 12, 12, 8, 8],
[8, 12, 12, 8, 8]],
[[4, 6, 6, 4, 4],
[4, 6, 6, 4, 4],
[4, 6, 6, 4, 4]]]], dtype=np.int32)
np.testing.assert_array_equal(dx_value_expected, dx_value_obtained)

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tests/st/ops/cpu/test_pad.py
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